Abstract: A low-pass filter, including: between a first terminal and a second terminal, a series association of a first resistor, of a second resistor, and of a first amplifier; in parallel with the second resistor, a series association of a second amplifier and of a first capacitor; a second capacitor between an input of the first amplifier and a third terminal of application of a reference voltage; and a third capacitor between the second terminal and the third terminal.

Abstract: An analog finite impulse response (AFIR) filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter.

Abstract: An etching mask, comprising the delineation pattern of the gate electrode, of a source contact, a drain contact and a counter-electrode contact, is formed on a substrate of semi-conductor on insulator type. The substrate is covered by a layer of dielectric material and a gate material. The counter-electrode contact is located in the pattern of the gate electrode. The gate material is etched to define the gate electrode, the source contact and drain contacts and the counter-electrode contact. A part of the support substrate is released through the pattern of the counter-electrode contact area. An electrically conductive material is deposited on the free part of the support substrate to form the counter-electrode contact.

Abstract: A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an enable circuit. Information related to the mapping between each physical register and an appropriate architecture register is obtained from a physical register mapping table (PRMT) by one and only one collection circuit during only one of a fourth number of instruction cycles. Each decode circuit has its input coupled to the output of one different collection circuit and is capable of converting its input into a third number bit wide binary string selection code at its output. Each selection circuit is configured to receive from each selection code a bit from a bit position associated with that selection circuit. The enable circuit is configured to appropriately enable mapping of information from the PRMT to the ARMT.

Abstract: A multimode filter that is versatile for digital signal processing including in-loop processing (de-blocking and de-ringing), post processing (de-blocking and de-ringing), and overlap smoothing. A flexi-standard filter includes the multimode filter. An electronic device includes the flexi-standard filter. A process for digital signal processing includes in-loop processing (de-blocking and de-ringing), post processing (de-blocking and de-ringing), and overlap smoothing.

Abstract: A fuel cell device includes a housing containing a fuel processor that generates fuel gas and a fuel cell having electrodes forming an anode and cathode, and an ion exchange electrolyte positioned between the electrodes. The housing can be formed as first and second cylindrically configured outer shell sections that form a battery cell that is configured similar to a commercially available battery cell. A thermal-capillary pump can be operative with the electrodes and an ion exchange electrolyte, and operatively connected to the fuel processor. The electrodes are configured such that heat generated between the electrodes forces water to any cooler edges of the electrodes and is pumped by capillary action back to the fuel processor to supply water for producing hydrogen gas. The electrodes can be formed on a silicon substrate that includes a flow divider with at least one fuel gas input channel that can be controlled by a MEMS valve.

Abstract: An image capture unit and its manufacturing method. The image capture unit includes a thinned-down integrated circuit chip having an image sensor on its upper surface side. A wall extends above a peripheral upper surface ring-shaped area, and a lens rests on the high portion of the wall.

Abstract: A method and a circuit for scrambling an RSA-CRT algorithm calculation by an electronic circuit, in which a result is obtained from two modular exponentiation calculations, each providing a partial result, and from a recombination step, and in which a first step adds a digital quantity to at least one first partial result before said recombination step; and a second step cancels the effects of this quantity after the recombination step.

Abstract: The invention relates to a method of bit allocation in a scene change situation during encoding a video sequence. Following a scene change, the picture complexity of the current picture is adjusted so that the bit allocation for the next picture is more accurately estimated.

Abstract: A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states.

Abstract: Methods and systems are described for displaying enabling the transmission, formatting, and display of multimedia data after a hot plug event during a start-up dead period. In particular, approaches for transmission, formatting, and display of multimedia data in the absence or non-operation of a hot plug detect system or signal, so that multimedia information can be displayed in a proper format even during the dead period when no hot plug detect signal is received.

Abstract: A system for processing a received signal having at least one code applied thereto, the received signal having a frequency, the system comprising: first correlator circuitry arranged to correlate the received signal with a first code to provide an output; second correlator circuitry arranged to correlate the received signal with a second code to provide an output, wherein the first code and the second code are different; and processor for processing together the outputs of the first and second correlator circuitry to cancel the frequency.

Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench including an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer including nitrogen or carbon.

Abstract: A method and apparatus for determining the attitude of an object is provided herein. The method for determining the attitude of the object comprises: receiving a gravity acceleration signal and a geomagnetic field signal, the gravity acceleration signal and the geomagnetic field signal changing with the attitude of the object accordingly; determining a gravity field representation in an object coordinate system according to the gravity acceleration signal, and determining a geomagnetic field representation in the object coordinate system according to the geomagnetic field signal; calculating a conversion parameter of coordinate system between to the object coordinate system and a terrestrial coordinate system according to the gravity field representation and the geomagnetic field representation in the object coordinate system; and determining the attitude of the object according to the conversion parameter of coordinate system.

Abstract: An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.

Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.

Abstract: A system for adjusting the perceived depth of 3D content in response to a viewer input control signal. The system comprises: 1) a content source providing an input left stereoscopic image and an input right stereoscopic image; 2) a disparity estimator to receive the input left and right stereoscopic images, detect disparities between the input left and right stereoscopic images, and generate a disparities array; and 3) processing circuitry to fill in occlusion areas associated with the disparities array and apply a scale factor to the detected disparities to thereby generate a scaled disparities array. The system further comprises a warping engine to receive the scaled disparities array and generate an output left stereoscopic image and an output right stereoscopic image. The output left and right stereoscopic images have a different perceived depth than the input left and right stereoscopic images.

Abstract: A method is for monitoring the electrical integrity of lines of photosites of an imaging device with matrix array of photosites. The control lines of photosites may include for each line of photosites an emission of elementary electrical control signals for the photosites of the line. The method may include diagnosis of the elementary electrical control signals emitted.

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

Abstract: A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.