Abstract: A sensing method is used for a capacitive sensing device, wherein the capacitive sensing device has a plurality of capacitive sensing components, each of which is charged or discharged by a charging component respectively. The sensing method comprises the steps of: a first sampling step of sampling at least one of charging or discharging time of a capacitive sensing component of the plurality of capacitive sensing components to determine a first sample time for the component sampled, wherein the component sampled and at least one another component of the plurality of capacitive sensing components are charged or discharged simultaneously during the first sampling step; a first comparing step of comparing the first sample time for the component sampled with a reference time; and an outputting step of outputting a trigger signal in the event that the first sample time exceeds the reference time.

Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.

Abstract: A thermoelectric generator including, between first and second walls delimiting a tightly closed space, a layer of a piezoelectric material connected to output terminals; a plurality of openings crossing the piezoelectric layer and emerging into first and second cavities close to the first and second walls; and in the tight space, drops of a liquid, the first wall being capable of being in contact with a hot source having a temperature greater than the evaporation temperature of the liquid and the second wall being capable of being in contact with a cold source having a temperature smaller than the evaporation temperature of the liquid.

Abstract: A method of processing information to be confidentially transmitted from a first module to a second module provides that a first scalar multiplication may be carried out in order to obtain a first result [r]P. This first scalar multiplication comprises a plurality of generation steps of ordered factors from which a plurality of first partial sums are required to be built. The method also comprises the carrying out of a second scalar multiplication in order to obtain a second result. This second multiplication provides that a plurality of second partial sums may be built. A piece of encrypted information is obtained by processing the information based on the results of the scalar multiplications. The second partial sums of the second scalar multiplication use the same ordered factors obtained by the generation step of the first scalar multiplication.

Abstract: A switching circuit includes a source follower current mirror having an input, an output, a first source terminal, a bias terminal, and a second source terminal; a current source coupled to the input of the current mirror; an output terminal coupled to the output of the current mirror; a first bias transistor coupled to the first source terminal; a second bias transistor coupled to bias terminal of the current mirror; and a driver transistor coupled to the second source terminal. An input transistor in the current mirror is sized such that the input voltage is substantially independent of the supply voltage.

Abstract: A method for manufacturing a phase change memory includes forming a phase change memory cell by forming a phase change layer between two switching layers. The phase change layer is separated from thermal heat sinks, such as the bitline or wordline, by the switching layers.

Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Abstract: A MEMS gyroscope includes: a microstructure having a fixed structure, a driving mass, movable with respect to the fixed structure according to a driving axis, and a sensing mass, mechanically coupled to the driving mass so as to be drawn in motion according to the driving axis and movable with respect to the driving mass according to a sensing axis, in response to rotations of the microstructure; and a driving device, for keeping the driving mass in oscillation with a driving frequency. The driving device includes a discrete-time sensing interface, for detecting a position of the driving mass with respect to the driving axis and a control stage for controlling the driving frequency on the basis of the position of the driving mass.

Abstract: A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Abstract: A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential block to generate delayed test patterns. The delayed test patterns are passed to the shadow logic block for testing faults.

Abstract: A signal processor for processing a digital input signal including samples sampled at a sampling frequency, the signal processor comprising a plurality of filters arranged to divide the digital input signal into a first signal in a first frequency band below a first cut-off frequency, and a second signal in a second frequency band above a second cut-off frequency; first frequency shifting circuitry arranged to shift the second signal to a frequency band below the first cut-off frequency; decimation circuitry arranged to decimate the first signal and the shifted second signal; and processing circuitry arranged to process the decimated first and second signals.

Abstract: A detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

Abstract: A mold is for obtaining, on a substrate, an array of carbon nanotubes with a high control of their positioning. The mold includes a first layer of a first preset material having a surface having in relief at least one first plurality of projections having a free end portion with a substantially pointed profile.

Abstract: Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.

Abstract: A system and method involving a read channel pipeline having a plurality of vector sequencers that may be used to control the processing blocks. In one embodiment, a read channel pipeline may include processing blocks that may be controlled a command word provided by vector sequencers. Incoming data may be delineated by identifying an early period, a steady-state period, and a trailing period. Instead of controlling these blocks with a static state machine controller, a plurality of vector sequencers are coupled to the plurality of processing blocks. Thus, a first vector sequencer may control the processing blocks during the early period and the steady state period, but then hand off control to a second vector sequencer for the trailing period. Using vector sequencers for implementing command words allows for greater programming flexibility once the device has been manufactured and deployed for use.

Abstract: A harmonic rejection mixer includes a differential in-phase signal path and a differential quadrature signal path, a shared differential transconductor for generating a shared transconductor output signal from a mixer input signal, a first selective mixing circuit disposed in the differential quadrature signal path and coupled to the shared differential transconductor, and a second selective mixing circuit disposed in the differential in-phase signal path and coupled to the shared differential transconductor, the first selective mixing circuit is controlled by a first selective control signal and the second selective mixing circuit is controlled by a second selective control signal to selectively supply the shared transconductor output signal to the differential quadrature signal path and the differential in-phase signal path, respectively.

Abstract: A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.

Abstract: Systems and methods for creating carbon nanotubes are disclosed that comprise a growing a nanotube on a tri-layer material. This tri-layer material may comprise a catalyst and at least one layer of Ti. This tri-layer material may be exposed to a technique that is used to grow a nanotube on a material such as a deposition technique.

Abstract: A circuit includes a comparator having input terminals configured to be coupled across a drive transistor adapted to drive a phase of a motor. The comparator senses a drive current of the motor phase, said sensed drive current represented by a periodic signal whose period is indicative of motor speed. A motor speed calculation circuit receives the periodic signal and processes the periodic signal to determine a speed of the motor.