Abstract: Corruption in a key stored in a memory is detected by reading a key from a key memory and determining if detection bits of the key read from the key memory correspond to an expected value. The expected value is a value of the detection bits of the key when the key is written to the key memory.

Abstract: A method and integrated circuit for preserving a battery's charge and protecting electrical devices is disclosed. A maximum and a minimum battery voltage value at the output port are stored in a memory. A steady state battery voltage at the output port is measured and stored in the memory. A processor compares the measured steady battery voltage value to the maximum and the minimum battery voltage values. If the measured steady state battery voltage value is greater than the maximum battery voltage value, an over voltage state is reported by the processor. If the measured steady state battery voltage value is less than the minimum battery voltage value, a low battery voltage state is reported by the processor.

Abstract: A method and audio device are presented that preserve mono energy during downmixing of a hybrid coding process of an audio signal. The method includes calculating a stereo scaling factor in a group level that is definable within a stereo band. The method may also include updating the stereo scaling factor using an update rate and synchronizing the update rate of a spatial parameter during a fast changing transient portion of the signal. A number of groups in a first stereo band may be greater than a number of groups in a second stereo band, and the first stereo band may be a lower frequency band than the second band or may be perceptually more important than the second band.

Abstract: An embodiment of a voltage converter includes: voltage-transformer means having a primary side, designed to receive an input voltage, and a secondary side, designed to supply an output voltage; control-switch means coupled to said primary side; and a control circuit, coupled to a control terminal of said control-switch means and designed to control switching thereof as a function of a first signal correlated to said output voltage; said control circuit being provided with an error-amplifier stage, designed to process a difference between said first signal and a reference signal, wherein said error-amplifier stage is configured so as to have a transconductance characteristic with a linear-operation region, having a given slope, and at least one first clamped region, which has a slope lower than said given slope and is contiguous to said linear-operation region.

Abstract: A self-coexistence window reservation protocol for a plurality of Wireless Regional Area Network (WRAN) cells operating in a WRAN over a plurality of channels includes a sequence of self-coexistence windows that uniquely identifies a transmission period for each WRAN cell. A self-coexistence window reservation protocol is included within the first packet of a Coexistence Beaconing Protocol period identifying when each WRAN cell associated with a particular channel will transmit. When not actively transmitting, a WRAN cells remains in a passive, receiving mode to accept data. As the transmissions of each WRAN cell operating on a particular channel are scheduled, contention for a transmission period is eliminated.

Abstract: A method of performing transactions in a communication network in which is exchanged between Intellectual Property (IP) cores has information transported in packets which include a header for transporting control information and one or more payloads transporting content. A versatile packet format is used which is adapted to transport different traffic patterns generated by the IP cores using different protocols for simple interoperability between the IP cores and also providing configurability of the granularity arbitration process to correct crossing the routers in the communication network.

Abstract: A device generates a signal representative of a current flowing through a load inductor of a converter, the converter having a first transformer including a primary winding driven with a pulse width modulated (PWM) voltage signal. The device may include a sense inductor magnetically coupled to the load inductor, and an integrator configured to integrate a voltage drop on the sense inductor and to generate a first signal representative of the current flowing through the load inductor with an offset. The device may further include a second transformer to be magnetically coupled to the primary winding of the first transformer and generating a second signal representative of a current flowing through the primary winding, and a peak detector configured to sample and hold a peak value of the second signal at every cycle of the PWM voltage signal.

Abstract: An embodiment of a voltage converter, designed to convert an input voltage into a regulated output voltage, having: a voltage transformer having a primary winding receiving the input voltage, a secondary winding supplying the output voltage (Vout), and an auxiliary winding supplying a feedback signal correlated to the output voltage; a control switch, connected to the primary winding; and a control circuit, connected to a control terminal of the control switch for controlling switching thereof as a function of the feedback signal. The control circuit is provided with a sampling stage that samples the feedback signal and supplies a sampled signal. An averager stage is connected to the output of the sampling stage and implements a low-pass filtering of the sampled signal so as to reduce undesirable oscillations due to sampling.

Abstract: An optical navigation device may include an image sensor with an imaging surface, a laser, and an optical waveguide layer having an exposed user surface and a total internal reflection (TIR) surface on the underside of the exposed user surface. The waveguide layer, the laser, and the image sensor may be together arranged to direct radiation emitted by the laser onto the imaging surface at least partly by total internal reflection by the TIR surface.

Abstract: The present disclosure relates to a method for controlling a touch pad, comprising an object locate mode for locating an object on the touch pad comprising steps of: determining a measurement of capacitance of each of the pairs of electrodes of the touch pad, each pair comprising a row electrode and a column electrode transverse to the row electrode, comparing each measurement with a first detection threshold, and if the comparison of at least one measurement with the first threshold reveals the presence of an object on the touch pad, locating the object on the touch pad according to the capacitance measurements, the method comprising a proximity detection mode comprising steps of: determining a measurement representative of the capacitance between one or two electrodes and one or two other electrodes of the touch pad, and comparing a measurement obtained with a second detection threshold different from the first threshold.

Abstract: A method for controlling a contact angle between a glue and a surface of a substrate during manufacture of microchip packages is disclosed. The method includes applying a glue to a surface of a substrate, and placing an electrode in electrical connection with the glue. A potential difference is applied between the electrode and the substrate. The potential difference is applied across the glue and causes a contact angle between the glue and the surface of the substrate to be altered.

Abstract: A circuit simulator includes at least one clock generator. The at least one clock generator is configured to generate at least one root clock signal for an associated clock domain part of the circuit under simulation. The circuit simulator also includes a clock modifier configured to generate at least one delay to be applied to at least one of the at least one root clock signal.

Abstract: A semiconductor thermoelectric cooler includes P-type and N-type thermoelectric cooling elements. The P-type and N-type thermoelectric elements have a first portion having a first cross-sectional area and a second portion having a second cross-sectional area larger than the first cross-sectional area. The P-type and N-type thermoelectric cooling elements may, for example, be T-shaped or L-shaped. In another example, the thermoelectric cooling elements have a first surface having a first shape configured to couple to a first electrical conductor and a second surface opposite the first surface and having a second shape, different from the first shape, and configured to couple to a second electrical conductor. For example, the first surface may have a rectilinear shape of a first area and the second surface may have a rectilinear shape of a second area different from the first area. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract: A semiconductor thermoelectric cooler is configured to direct heat through channels of the cooler. The thermoelectric cooler has multiple electrodes and a first dielectric material positioned between side surfaces of the electrodes. A second dielectric material, different from the first dielectric material, is in contact with top surfaces of the electrodes. The first dielectric material extends above the top surface of the electrodes, separating portions of the second dielectric material, and is in contact with a portion of the top surfaces of the electrodes. The first dielectric material has a thermal conductivity different than a thermal conductivity of the second dielectric material. A ratio of the first dielectric material to the second dielectric material in contact with the top surface of the electrodes may be selected to control the heat retention. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: A copper interconnect structure has an intrinsic graphene cap for improving back end of line (BEOL) reliability of the interconnect by reducing time-dependent dielectric breakdown (TDDB) failure and providing resistance to electromigration. Carbon atoms are selectively deposited onto a copper layer of the interconnect structure by a deposition process to form a graphene cap. The graphene cap increases the activation energy of the copper, thus allowing for higher current density and improved resistance to electromigration of the copper. By depositing the graphene cap on the copper, the dielectric regions remain free of conductors and, thus, current leakage within the interlayer dielectric regions is reduced, thereby reducing TDDB failure and increasing the lifespan of the interconnect structure. The reduction of TDDB failure and improved resistance to electromigration improves BEOL reliability of the copper interconnect structure.

Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plu

Abstract: A monitoring system includes an array of concatenated sensing nodes, with each sensing node being configured to have at least one of near-field and far-field RF coupling circuitry to interface with an adjacent sensing node. A respective device is coupled to each of the sensing nodes. A reader device is configured to have at least one of near-field and far-field RF coupling circuitry to interface with the array of concatenated sensing nodes to read data from the devices.

Abstract: A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein.

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.