Abstract: A mesa-type bidirectional Shockley diode including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of said regions of the first conductivity type, each buried region being complementary in projection with the other; and a groove arranged in the vicinity of the periphery of the component on each of its surfaces, the component portion external to the groove comprising, under the external portion of the upper and lower regions of the second conductivity type, regions of the first conductivity type of same doping profile as said buried regions.

Abstract: Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop.

Abstract: Multiple virtual MAC addresses may be added to WGA devices that may have different traffic streams to another device that requires different services, thus creating distinct MAC and device level implications. Beamforming training can be done at the device level for all virtual MAC addresses. Wakeup, doze, and ATIM power save can be done at the device level depending on the frames received. Authentication, deauthentication, association, and deassociation can be done variously at both levels. Further MSDUs can be aggregated for the multiple MAC addresses.

Abstract: The invention relates to a driver circuit used to transmit a digital signal from a source device to a destination device. The driver circuit provides a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. In the circuit, a pair of first switches of a first plurality are coupled in parallel between a first current node and respective ones of first and second output terminals. A plurality of pairs of second switches of a second plurality are coupled in parallel between a respective second current node and the first and second output terminals. Timing circuitry applies input signals to the pair of first switches and successive input signals to the pairs of second switches so as to develop a staggered voltage across a load coupled between the first and second output terminals.

Abstract: A monitoring device is for monitoring physical characteristics of a building material. The monitoring device is buried inside a block of the building material, and has a sensor to sense physical characteristics thereof. The sensor transmits a signal representative of the physical characteristics.

Abstract: An optical range finder includes a light source adapted to produce illumination which impinges on a target. A detector receives a reflection of the illumination from the target, and a range code generator generates from the detected reflection a range code indicative of the range of the target from the range finder for each pulse. A signal processor receive plural range codes over a predetermined interval. A content addressable memory is used to count how many identical range codes are received during the predetermined interval. An identification is then made of the range code with the highest count, and that range code with the highest count is output as indicative of the range of the target from the range finder.

Abstract: A keyboard may include a plurality of optical keys. Each optical key may include an optical module and an interaction surface. The optical key may be configured to be activated based on movement of an object on or adjacent the interaction surface. Each movement may produce a different output from the optical module to thereby generate a predetermined input for a device.

Abstract: A circuit for converting a measured variable capacitance to an output voltage signal includes a charge amplifier circuit selectively coupled to an integrator circuit. The charge amplifier circuit, in one implementation, is configured as a high pass filter. In another implementation, the charge amplifier circuit is configured as a combination high pass and low pass filter. The charge amplifier circuit is selectively coupled to the integrator circuit when the circuit forces a switch in voltage across a measurement capacitor.

Abstract: A mesa-type bidirectional Shockley diode delimited on its two surfaces by a peripheral groove filled with a glassivation including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of the regions of the first conductivity type, at the interface between the substrate and the corresponding layer of the second conductivity type, each buried region being complementary in projection with the other; and a peripheral ring under the external periphery of each of the glassivations, of same doping profile as the buried regions.

Abstract: A circuit for converting an A.C. power supply voltage into a D.C. voltage, including: a first branch capable of providing a first power level; and a second parallel branch capable of providing a second power level greater than the first one, the second branch including a bidirectional activation switch.

Abstract: A shadow hardware system and method is provided. The shadow hardware system provides an interface between an access device and shadowed devices. Shadowed devices are devices that the shadow hardware system provides an interface to the access device although the shadowed device may not actually be present or available to the access device, such as implementing a disk drive as flash memory. The access device, such as a host processor, issues requests to a disk drive and the shadow hardware system converts the requests to requests suitable for the flash memory. A shadow remapper redirects the requests to shadow registers and notifies the shadow controller of the pending request. The shadow controller accesses the shadow registers and modifies the registers (if necessary) before forwarding the registers to the actual hardware devices. Any suitable device may be shadowed.

Abstract: A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions.

Abstract: A clock circuit includes a frequency or phase comparator for receiving a reference clock signal, an LC VCO coupled to the comparator, a feedback divider coupled between the LC VCO and the comparator, a clock distribution chain coupled to the feedback divider and the first VCO, and a DLL or injection-locked ring-VCO coupled to the clock distribution chain for providing a plurality of phased output clock signals.

Abstract: One or more digital video frames are interpolated using motion compensated temporal interpolation (MCTI). The quality of motion vectors corresponding to object motion between the two adjacent second video frames is detected. An average of forward motion vectors and an average of backward motion vectors representing motion of the object are compared by calculating the absolute value difference of the averaged forward and backward motion vectors to detect the quality of the motion vectors and a control signal is generated corresponding to the detected quality. Customized Image segmentation based on a first mode of image processing, a second mode of image processing or a combination of the first and second modes of image processing is then performed based on the detected accuracy to generate the interpolated frame.

Abstract: A sync signal generator for a capacitive sensor includes a charge amplifier having an input for coupling to an inactive receive line in the capacitive sensor, a first comparator having a first input for receiving a first threshold voltage, a second input coupled to an output of the charge amplifier, and an output for providing a first sync signal, and a second comparator having a first input for receiving a second threshold voltage, a second input coupled to the output of the charge amplifier, and an output for providing a second sync signal. The charge amplifier includes an operational amplifier having a feedback circuit including a capacitor and a switch. The first threshold voltage is provided by a first digital-to-analog converter, and the second threshold voltage is provided by a second digital-to-analog converter.

Abstract: A cache memory comprises a first set of storage locations for holding syllables and addressable by a first group of addresses; a second set of storage locations for holding syllables and addressable by a second group of addresses; addressing circuitry operable to provide in each addressing cycle a pair of addresses comprising one from the first group and one from the second group, thereby accessing a plurality of syllables from each set of storage locations; and selection circuitry operable to select from said plurality of syllables to output to a processor lane based on whether a required syllable is addressable by an address in the first or second group.

Abstract: An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Abstract: The embodiments of the present disclosure teach overlaying videos on a display device. The technique involves one or more buffers at input such as a first buffer (Primary Buffer) and an overlay buffer, a blitting module, a second buffer(Frame Buffer), and a display screen. The first buffer provides a first image data to the blitting module and the overlay buffer provides a second image data to the blitting module. The embodiments of the present disclosure demonstrate overlaying the second image on the first image with enhanced configurable functionality (like stretching, clipping, color keying, Alpha Blending and Raster Operation) if required, without modifying the Primary Buffer without the need of any overlay support in hardware.

Abstract: An electronic synchronous/asynchronous transceiver device for power line communication networks is integrated into a single chip and operates from a single supply voltage. The transceiver device includes: at least an internal register that is programmable through a synchronous serial interface; at least a line driver for a two-way network communication over power lines implemented by a single ended power amplifier with direct accessible input and output lines that is part of a tunable active filter for the transmission path; and at least a couple of linear regulators for powering with different voltage levels different kind of external controllers linked to the transceiver device.

Abstract: A method is provided for reading a captured image, with the captured image comprising at least first and second parts and a border area positioned between the first and second parts. Converted pixels are obtained by applying digital-to-analog conversion to the pixels in the captured image, and the converted pixels corresponding to the border area of the captured image are stored in a buffer. A first set of processed pixels is obtained by applying image processing to the converted pixels corresponding to the first part of the image and to the converted pixels stored in the buffer, and a second set of processed pixels is obtained by applying image processing to the converted pixels corresponding to the second part of the image and to the converted pixels stored in the buffer. A processed image is provided by combining the first and second sets of processed pixels. Also provided is a processing device for reading a captured image.