Abstract: A control circuit for a full-bridge-stage to drive an electric load includes PWM generation circuitry for generating first and second PWM signals so that a difference between duty-cycles of the PWM signals represents an amplitude of a drive current. A logic XOR gate is input with the first and second PWM signals and generates a logic XOR signal. A logic sampling circuit generates a logic driving command of a half-bridge stage, a logic value of which corresponds to a sign of the drive current, by sampling one of the first and second PWM signals based upon active switching edges of the logic XOR signal. A second XOR gate generates a third PWM driving signal of the other half-bridge of the full-bridge stage, a duty-cycle of which corresponds to the amplitude of the drive current.

Abstract: The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set.

Abstract: A communication system includes interfacing between a first synchronous circuit and a second synchronous circuit. The system includes a first interface system and a second interface system. The first interface system receives data from the first synchronous circuit, and encodes the data according to an asynchronous communication protocol. The encoded data are transmitted over a communication channel to the second interface system. The second interface system decodes the data and transmits the decoded data to the second synchronous circuit. The first interface system includes a first FIFO memory for storing temporarily the data received from the first synchronous circuit and the second interface system includes a second FIFO memory for storing temporarily the data transmitted over the communication channel.

Abstract: Switch including a terminal of a first type and at least two terminals of a second type, and a number of circuits capable of ensuring exclusive connection of one of the terminals of the second type to the terminal of the first type as a function of a set of control orders wherein the terminal of the first type is connected to a common point by a first circuit; each terminal of the second type is connected to the common point by a second circuit, with each second circuit including a portion that is magnetically coupled to the first circuit, a static switch mounted in parallel with the portion and capable of being controlled in the “off” state in order to connect the terminal of the first type to the terminal of the second type associated with the second circuit in question.

Abstract: A circuit for generating a reference voltage including: a first current source in series with a first bipolar transistor, between a first and a second terminal of application of a power supply voltage; a second current source in series with a second bipolar transistor and a first resistive element, between said first and second terminals, the junction point of the first resistive element and of the second bipolar transistor defining a third terminal for providing the reference voltage; a follower assembly having an input terminal connected between the first current source and the first bipolar transistor, and having an output terminal connected to a base of the second bipolar transistor; and a resistive dividing bridge between the output terminal of the follower assembly and said second terminal, the midpoint of this dividing bridge being connected to a base of the first bipolar transistor.

Abstract: An interface system for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal, a first data signal when a first control signal indicates that the first data signal contains valid data, and wherein the asynchronous circuit generates a second data signal according to an asynchronous communication protocol. The system includes a FIFO memory, a control circuit for asynchronously writing the second data signal in the memory when the second data signal indicates the start of a communication, and synchronously reading the second data signal from the memory in response to a clock signal, and a conversion circuit for decoding, according to a asynchronous communication protocol, the second data signal read from the memory in a decoded data signal, wherein the decoded data signal corresponds to the first data signal.

Abstract: An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information.

Abstract: A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

Abstract: PCR device (1) comprising at least a chamber (2), the chamber (2) being delimited on one side by a PCR substrate (3) at least partially covered by a polyelectrolyte coating (4) forming hydrophilic regions. The polyelectrolyte coating comprises at least one layer facing the chamber (2), the layer being a negatively charged polyelectrolyte layer. Further a hydrophobic polymer layer may be applied onto the PCR substrate facing the chamber forming hydrophobic regions delimiting the hydrophilic regions. Further a method for passivating a PCR substrate comprising the step of applying a polyelectrolyte is provided for.

Abstract: An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation.

Abstract: A comparator having first and second stages can provide component offset compensation and improved dynamic range. The first stage can receive first and second input signals and produce first and second output signals. The second stage can be coupled to the first stage to receive the first and second output signals at first and second input terminals of the second stage. The second stage can provide a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. The comparator is operable to receive input voltages that reach the supply voltage.

Abstract: A directional anti-aliasing filter circuit includes an input node and an output node, a directional anti-aliasing filter having an input coupled to the input node, an adaptive gain control having an input coupled to an output of the directional anti-aliasing filter, a summer having a first input coupled to an output of the adaptive gain control, a second input coupled to the input node, and an output coupled to the output node, a texture detector for providing a texture adjust signal to the directional anti-aliasing filter and a texture adaptive gain signal to the adaptive gain control, an edge detector for providing an edge direction signal to the directional anti-aliasing filter, and a corner detector for providing a corner adaptive gain signal to the adaptive gain control.

Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

Abstract: A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.

Abstract: A moving device to move across a surface including a motor rolling motion apparatus is disclosed. The moving device is coupled to the motor and has a body with an outer surface. A dense population of fibrils protrudes from the outer surface, with each fibril having a free-end termination configured to establish adhesion to the surface by inter-molecular Van der Waals forces.

Abstract: An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.

Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.

Abstract: A semiconductor subassembly, a modular sidewall element having modular dimensions that accommodates placement of the semiconductor subassembly in a modular layout and a semiconductor substrate base element coupled to the modular sidewall element. The semiconductor substrate base element has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element and the semiconductor substrate base element configured to form a base of the semiconductor subassembly.

Abstract: A thermometer coded line is configured to convert a time interval to a digital code for subsequent processing in order to output a value representative of said time interval. A digital peak detector is coupled to receive output from the thermometer coded line, the detector operating for correction of an undesired code of said digital code in order to ensure a valid output of said value. A majority logic circuit is coupled between the thermometer coded line and the digital peak detector, the logic circuit operating for correction of undesired code of said digital code in order to ensure the valid output of said value. The detector functions to correct any undesired code not corrected by, or introduced by, the logic circuit.

Abstract: A semiconductor device includes an assembly of two integrated circuits. The assembly has a layer of photoresist filling the space between the two integrated circuits, and at least one electrically conducting pillar within the resist and electrically coupling the two integrated circuits.