Abstract: A current-steering digital-to-analog converter may include a plurality of current cells. Each current cell may comprise a dual bias switched cascode output current source/sink, a bias source, complementary bias switching elements coupled between the bias source and the bias inputs of the switched cascode output current source/sink, and complementary switching signals coupled to the control inputs of the complementary bias switching element.

Abstract: A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops.

Abstract: System for testing a multitasking computation architecture, comprising a set of processors linked by data communication channels, comprising a generating stage for generating sequences of test instructions based on characteristics of said processors comprising programming rules for the computation processors, characterized in that it comprises a control stage for the stage for generating sequences based on data representative of the data communication channels.

Abstract: Disclosed is a fluoresceine derivative having the following formula: for the production of an electronic device, in particular a memory switch.

Abstract: A microelectromechanical device that includes a fixed supporting body, at least one semiconductor body, which is movable with respect to the fixed supporting body, and at least one micromotor for moving the semiconductor body with respect to the fixed supporting body, the micromotor having at least one permanent magnet and a coil, which are coupled together and are movable with respect to one another. A ferromagnetic guide is coupled to the magnet and is shaped so as to concentrate lines of magnetic field generated by the magnet towards the coil.

Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.

Abstract: A semiconductor product includes a portion made of copper, a portion made of a dielectric and a self-aligned barrier between the copper portion and the dielectric portion. The self-aligned barrier includes a first copper silicide layer comprising predominantly first copper silicide molecules, and a second copper silicide layer comprising predominantly second copper silicide molecules. The proportion of the number of silicon atoms is higher in the second silicide molecules than in the first silicide molecules. The second copper silicide layer is positioned between the copper portion and the first copper silicide layer. A nitride layer may overlie at least part of the first copper silicide layer.

Abstract: A method and a circuit for decoding a coded signal including a first decoding system capable of receiving the coded signal and of providing a first signal comprising portions considered correct and a second decoding system capable of providing a second signal from the coded signal and from portions considered correct of the first signal.

Abstract: A control apparatus for a supply device of a load, the supply device is of switching type and connected between a supply voltage and a reference voltage, the apparatus including a sigma-delta device having an input terminal at which is present a first digital signal and adapted to provide a pulse-density modulation signal at the output terminal; the sigma-delta device including a feedback circuit capable of sending to the input terminal of the sigma-delta device a second digital signal whose value depends on the value of the output signal, and the apparatus including a device capable of digitalizing the supply voltage and of providing a further digital signal. The feedback circuit includes a terminal capable of receiving the further digital signal, and the sigma-delta device having a gain such that the output digital signal is proportional to the inverse of the further digital signal.

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: A decoder apparatus for decoding a first input set of demodulated data elements obtained by demodulating transmitted data elements received over a transmission channel so as to obtain a corresponding output set of decoded data elements. The decoder apparatus includes a first register a first selector coupled to the first register, a second selector coupled to the second register, and a combiner coupled to the first and the second selection circuits and operable to combine selected demodulated data elements with selected channel description elements. The decoder apparatus still further includes a controller coupled to the first and second selectors and to the combiner, that is adapted to generate a plurality of signals defining a control sequence for driving the first and second selectors and the combiner. Said controller is adapted to be configured so as to generate at least two control sequences according to the selected transmission diversity scheme.

Abstract: In a fingermouse image sensor, an array of radiation sensitive pixels is formed on an image sensing die at a position where the array of radiation sensitive pixels is formed off-center within the image sensing die. More specifically, the array of radiation sensitive pixels is formed as close as possible to an edge of the image sensing die. That image sensing die is mounted to a substrate at a position offset from a center of the substrate. More specifically, the image sensing die is positioned such that the edge of the image sensing die (where the array of radiation sensitive pixels is positioned) is adjacent an edge of the substrate.

Abstract: The perception of 3D sound positioning can be achieved using a 2D arrangement of speakers positioned around the listener. The disclosed techniques can enable listeners to perceive sounds as coming from above and/or below them, without the need for positioning speakers above and/or below the listener. In some embodiments, elevation information can be included in the X and Y horizontal components of the 2D ambisonics encoding. The X and Y components can be decoded using 2D ambisonics decoding. Suitable filtering may be performed on the decoded sound information to enhance the listener's perception of the elevation information encoded in the X and Y components.

Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure c

Abstract: A method of anisotropic plasma etching of a silicon wafer, maintained at a temperature from ?40° C. to ?120° C., comprising alternated and repeated steps of: etching with injection of a fluorinated gas, into the plasma reactor, and passivation with injection of silicon tetrafluoride, SiF4, and of oxygen into the plasma reactor, the flow rate of the gases in the plasma reactor being on the order of from 10% to 25% of the gas flow rate during the etch step.

Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.

Abstract: A method of filtering an image filter is disclosed. The filter is provided for a digital camera including image sensors sensitive to light, a color filter placed over sensitive elements of the sensors and patterned according to a Bayer mosaic pattern layout and an interpolation algorithm joining together the digital information provided by differently colored adjacent pixels in said Bayer pattern. The filter is adaptive and includes a noise level computation block for operating directly on a said Bayer pattern data set of for each color channel thus removing noise while simultaneously preserving picture detail.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: An integrated circuit includes at least one photosensitive element capable of delivering an electrical signal when light of at least one wavelength of the visible spectrum reaches it, and an electrooptic system functioning as an electrochemical shutter. The electrooptic system is located in the path of at least one light ray capable of reaching the photosensitive element and possesses at least one optical property, dependent on electrochemical reaction, that can be modified by an electrical control signal. The optical property is preferably transmission.

Abstract: A synchronous rectifier, including an energy storage element having a terminal; a power supply input, connected to the terminal of the storage element in a first time interval; a reference line connected to the terminal of the storage element in a second time interval; and a zero comparator, coupled to the terminal of the storage element to detect a current flowing in the energy storage element and disconnect the terminal of the storage element from the reference line upon detecting a zero current, the zero comparator having an offset and a propagation time; the zero comparator further having an offset control input and an output. An offset regulating loop is coupled between the output of the zero comparator and the offset control input and regulates the offset of the zero comparator to compensate the propagation time.