Abstract: The present invention relates to a process for the preparation of a composite polymeric material containing nanometric inorganic inclusions comprising the steps of: mixing a polymer with a thermolytic precursor to provide a homogeneous dispersion of said at least one precursor and of said at least one polymer; subjecting said homogeneous dispersion to heating to provide a molten polymer and thermolytic fission of the precursor, generating the inclusions dispersed in the molten polymer.

Abstract: A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device.

Abstract: A thyristor power control circuit reduces EMI and maintains a holding current in the thyristor to prevent flickering at a load. The power control circuit includes a thyristor configured to receive an input AC voltage, and responsive to a gate pulse generates a modified AC voltage. A rectifier receives the modified AC voltage and generates a rectified DC voltage. A power converter coupled to the rectifier receives the rectified DC voltage and generates a controlled output current. A damping circuit coupled to an output terminal of the rectifier includes a damping resistor for maintaining the holding current in the thyristor during an ON period of the thyristor. The damping circuit includes a first capacitor coupled in series to the damping resistor and a diode coupled in parallel to the damping resistor. The diode enables the first capacitor to discharge without causing power loss at the damping resistor.

Abstract: Detection of an anomalous event in an electronic apparatus includes detecting accelerations acting on the electronic apparatus, establishing a normal-mode range of accelerations that corresponds to normal operation of the apparatus, and detecting the anomalous event when a level of acceleration of the electronic apparatus exits the normal-mode range and remains outside the normal mode range for more than a defined duration. The method includes displacing the normal-mode range toward a current level of acceleration of the electronic apparatus while the level of acceleration remains outside the normal-mode range. Additionally, the normal-mode range is increased toward a maximum size while the level of acceleration remains outside the normal-mode range, and is decreased toward a minimum size while the level of acceleration is within the normal-mode range.

Abstract: An inductive coupling reader includes a passive interface circuit for modulating the impedance of an antenna circuit and extracting from the antenna circuit a data signal and a RF clock signal, and circuitry for coupling the reader to a removable security module. The reader includes an emulation circuit for opening a RF transmission channel with another reader, a non-removable electrical link linking the emulation circuit to the passive interface circuit, by which the data signal and the RF clock signal are supplied to the emulation circuit, and a data bus clocked by a bus clock signal having a frequency inferior to the frequency of the RF clock signal, for linking the emulation circuit to the removable security module. The reader has low electrical consumption.

Abstract: A lens barrel is mated with a lens mount through use of a screw thread whereby relative rotation adjusts lens focus. The lens barrel and lens mount are additionally provided with an interengaging formation that is interposed between an optical axis of the lens barrel and the screw thread. This formation provides a cylindrical sliding contact which isolates any particles produced by operation of the screw thread from reaching the optical components at or near the optical axis.

Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.

Abstract: A clock and data recovery method comprising the following steps: an oversampling step wherein an oversampled stream of samples is generated from an input data stream at a data rate by using reference clock signal at a clock rate, the clock rate being higher than the data rate, and a tracking step of the input data stream realised by locating transitions between adjacent samples of the oversampled stream and by moving a no transition area within the oversampled stream wherein no transitions between adjacent samples are found a recovered data signal being obtained as a central portion of the no transition area and a recovered clock signal being obtained by dividing the reference clock signal. A clock and data recovery device is also described.

Abstract: A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device.

Abstract: This invention relates to a method of receiving a first potentially unreliable clock signal having a first frequency; receiving a second reliable clock signal having a second frequency; wherein the first frequency and the second frequency have an expected relationship; determining whether the first potentially unreliable clock signal has changed with respect to the second reliable clock signal by: determining an actual relationship between the first potentially unreliable frequency and the second reliable frequency; and generating an alarm signal if the actual relationship is different to the expected relationship.

Abstract: Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.

Abstract: A method and a circuit for scrambling an RSA-CRT algorithm calculation by an electronic circuit, in which a result is obtained from two modular exponentiation calculations, each providing a partial result, and from a recombination step, and in which a first step adds a digital quantity to at least one first partial result before said recombination step; and a second step cancels the effects of this quantity after the recombination step.

Abstract: An embodiment of a telecommunications device includes means for providing a set of words, each word including a plurality of digital symbols; a first memory area for storing the set of words, the first memory area including a first sequence of memory locations each one for storing a symbol; a second memory area for storing a composite frame including a predetermined number of symbols, the second memory area including a second sequence of memory locations; conversion means for converting the set of words in the first memory area into the frame in the second memory area, the conversion means including reduction means for reducing each word by removing a set of symbols from the word according to a puncturing algorithm, and expansion means for expanding each word by adding a set of additional symbols to the word according to a repeating algorithm; and means for transmitting the frame.

Abstract: The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0<y?1) which have different respective Germanium contents, comprising the steps of: a) formation on a substrate covered with a plurality of Si1-yGey based semi-conducting zones (where 0<x<1 and x<y) and identical compositions, of at least one mask comprising a set of masking blocks, wherein the masking blocks respectively cover at least one semi-conducting zone of the said plurality of semi-conducting zones, wherein several of said masking blocks have different thicknesses and/or are based on different materials, b) oxidation of the semi-conducting zones of the said plurality of semi-conducting zones through said mask.

Abstract: A device for transforming an AC voltage to a lower AC voltage includes a generator of a PWM control signal and a first bidirectional switch to couple a load to the AC voltage during a conduction-phase. A second bidirectional switch discharges energy from the load during an off-phase of the first bidirectional switch. A first driving circuit of the first bidirectional switch is input with the PWM control signal and generates a first PWM signal, applied between control and conduction terminals of the first bidirectional switch. A second driving circuit for the second bidirectional switch is input with the PWM control signal and generates a second PWM signal, in phase opposition to the first PWM signal, applied between control and conduction terminals of the second bidirectional switch. An electric decoupling circuit is between the generator and second driving circuit. A transformer is between respective conduction terminals of the bidirectional switches.

Abstract: The method for block coding data, such as video data, via a compression operation includes applying to input-data blocks a discrete-cosine-transform (DCT) operation and a quantization operation to produce compressed-data blocks. The compressed-data blocks are subjected to a coding operation to obtain compressed output flows; and an inverse-quantization operation and an inverse-discrete-cosine-transform (IDCT) operation are applied on the compressed-data blocks to obtain reconstructed blocks. The method includes controlling generation of mismatch errors from the input-data blocks by detecting data blocks from the input-data blocks and compressed-data blocks that are liable to cause mismatch errors, and modifying the blocks that are liable to cause mismatch errors prior to the coding operation.

Abstract: A manual pointing device for a computer system, the device having at least one key that can be actuated manually by a user, and a click-event detection module coupled to the key for detecting actuation thereof. The click-event detection module is provided with an inertial sensor for detecting mechanical stresses generated by actuation of the key.

Abstract: An image sensor may have a pixel array and an imaging lens for forming an image on the pixel array. The sensor may also include a pixel readout unit for enabling individual pixel values to be readout. The sensor may further include a pixel selection unit wherein at least one pixel sub-array is selected according to the pixel values readout and the at least one sub-array is used for reading the image.

Abstract: Chemical-Mechanical Polishing can be used to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height. A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer.

Abstract: An integrated power MOSFET device formed by a substrate); an epitaxial layer of N type; a sinker region of P type, extending through the epitaxial layer from the top surface and in electrical contact with the substrate; a body region, of P type, extending within the sinker region from the top surface; a source region, of N type, extending within the body region from the top surface, the source region delimiting a channel region; a gate region; a source contact, electrically connected to the body region and to the source region; a drain contact, electrically connected to the epitaxial layer; and a source metallization region, extending over the rear surface and electrically connected to the substrate and to the sinker region.