Abstract: An integrated power MOSFET device formed by a substrate); an epitaxial layer of N type; a sinker region of P type, extending through the epitaxial layer from the top surface and in electrical contact with the substrate; a body region, of P type, extending within the sinker region from the top surface; a source region, of N type, extending within the body region from the top surface, the source region delimiting a channel region; a gate region; a source contact, electrically connected to the body region and to the source region; a drain contact, electrically connected to the epitaxial layer; and a source metallization region, extending over the rear surface and electrically connected to the substrate and to the sinker region.

Abstract: Information codes are arranged in pieces comprised of chunks of bytes over a network, such as a Peer-to-Peer overlay network, including a set of peer terminals. A first peer identifies missing chunks in the received pieces and requests such missing chunks from other peers. The chunks are subjected to a fountain code encoding wherein the chunks in a piece are X-ORed. The first peer is therefore capable of reconstructing a received piece encoded with fountain codes from a combination of linearly independent chunks corresponding to the piece. The chunks are transmitted over the network with a connection-less protocol, without retransmission of lost packets, preferably with a UDP protocol.

Abstract: The invention concerns a biasing circuit for controlling the current flowing through a differential pair (102, 104) comprising: a first branch comprising a first resistor (306), a first transistor device (308) and a second transistor device (310) coupled in series; a second branch comprising a second resistor (312), a third transistor device (314) and a fourth transistor device (316) coupled in series, a control node of the third transistor device being coupled to a first node (324) between the first resistor and the first transistor device, and a control node of the first transistor device being coupled to a second node (322) between the second resistor and the third transistor device; and an operational amplifier (318) having an output node coupled to control nodes of the second and fourth transistor devices, said output node providing a output signal (Vc) for controlling the current flowing through said differential pair.

Abstract: A system is disclosed for reducing artifacts in images and video, such as ringing or halo artifacts. The system may include an edge detector and a gain controller. The edge detector may create an edge image used by the gain controller to create a gain image, and the gain image may be used to reduce artifacts in an image. The gain controller may, for a current pixel in the edge image, compute the maximum value of the edge image over a window containing the current pixel. The gain controller may also perform averaging to determine a maximum edge value and a current edge value, and may also use a ratio of the current edge value and the maximum edge value to determine a gain to be applied to a pixel of an image.

Abstract: A current mode DC-DC controller operates with high efficiency even when the input and output voltages are close. Switches selectively connecting an input, ground and an output to inductor terminals are controlled in a buck/boost region to alternate between operation as a buck converter and operation as a boost converter. The number of switches repeatedly changing state is thus reduced, lowering switching losses and improving conversion efficiency. Current through the inductor during operation is sensed and compared to an error value to control switching from buck mode operation to boost mode operation and back.

Abstract: A method for producing an integrated device including a capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate, forming a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate, forming a second conductive layer including a second plate of the capacitor and functional connections to the functional circuits on a portion of the layer of insulating material corresponding to the dielectric layer, forming a protective layer of insulating material covering the second plate and the functional connections, forming a first contact for contacting the first plate, and forming a second contact and functional contacts for contacting the second plate and the functional connections, respectively, through the protective layer.

Abstract: An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are connected in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor.

Abstract: An embodiment of the invention relates to a power converter formed with an error amplifier and a related method. In an embodiment, a first switch is coupled in series with an error amplifier compensation capacitor. Upon detection of a current level greater than a threshold level, the compensation capacitor is decoupled from the error amplifier by opening the first switch. In an embodiment, a second switch is coupled in parallel with the compensation capacitor, and the current-sensing circuit enables conductivity of the second switch to discharge the compensation capacitor upon detection of the current level greater than the threshold level. The second switch is opened upon detection of the current level less than the threshold level. In an embodiment, the current-sensing circuit controls an output current of the power converter at a current-limit level upon detection of the internal current level greater than the threshold level.

Abstract: A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may include a controller configured to drive the first multiplexer and the second multiplexer respectively with a first select signal and a second select signal, a detection module configured to detect a phase difference between the first output signal and the second output signal and to generate a corresponding digital phase shift signal, the detection module including a phase comparator, and a Time-Digital converter circuit coupled thereto and having logic elements configured to generate the digital phase shift signal, and a logic circuit connected to the detection module and configured to process the digital phase shift signal and to generate a signal indicative of a control executed.

Abstract: A control device for a resonant converter, the control device including a first circuit to integrate at least one signal indicating a half wave of a current circulating in a primary winding of a transformer; the first circuit is structured to generate at least a control signal of the switching circuit depending on the integrated signal. The control device includes a second circuit to impose the equality of a switching-on time period of the first and second switches.

Abstract: Bistable carbazole compounds of formula (I) are described, wherein M is Fe, Co, Ru or Os, preferably Fe, useful as basic functional units for computing systems based on the QCA (Quantum Cellular Automata) paradigm; a process for their preparation is also described.

Abstract: An array of image sensors are connected in a daisy chained arrangement. The sensors in the array are addressed on the basis of the number of pixels each of them processes.

Abstract: A method for producing an integrated device including an MIM capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate; the first plate has a first melting temperature. The method further includes depositing a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate; the layer of insulating material is deposited at a process temperature being lower than the first melting temperature. The method further includes forming a second conductive layer including a second plate of the capacitor on a portion of the layer of insulating material corresponding to the dielectric layer. In the solution according to an embodiment of the invention, the first melting temperature is higher than 500° C.

Abstract: An embodiment for making a check of the electric type executed on wafer for testing the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on semiconductor wafer. An embodiment consists in making a current circulate in at least part of the seal ring of at least one of the above devices, and in case it has to flow in the seal ring of more devices, these seal rings are suitably interconnected to each other. Thanks to an embodiment the seal ring may also be reinforced in the angle areas of the chip, and suitable circuits may be possibly inserted in the seal ring or between the seal rings.

Abstract: A method of distributing media content over networks where content is shared includes coupling downloading metadata, which is accessed to start downloading media contents from the network, with semantic metadata representative of the semantic information associated with at least one of the content, and with source metadata indicative of the source of the media content. At least one of the semantic and the source metadata may be made accessible without downloading, even partially, the media content. A digital signature may also be applied to the metadata to enable the verification that, at reception, the metadata is intact and has not been subjected to malicious tampering.

Abstract: According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions.

Abstract: A mobile device includes a communications protocol stack including a MAC layer and TCP layer separated by an IP layer. A cross-layer coordination module parallel to the communications protocol stack is coupled to both the MAC layer and TCP layer. The MAC layer generates a message sent to the cross-layer coordination module indicating that the mobile device is about to engage in a communications handover from a first base station to a second base station. The cross-layer coordination module passes handover information to the TCP layer so as to inform the TCP layer of the communications handover. If the mobile device is operating as a TCP sender, the TCP layer freezes its connection and state during the communications handover. If the mobile device is operating as a TCP receiver, the TCP layer sends a TCP ACK message to a TCP sender having an advertised window size set to a zero value so as to cause the TCP sender to freeze a connection and state during communications handover.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring the content of a register, executing each of the micro-instructions, initializing a progress status of the saving/restoration of the registers, updating the progress status of the saving/restoration upon each generation of a micro-instruction for saving/restoring a register, saving the progress status in the event of an interruption in the saving/restoration of the registers to execute a higher-priority task, and restoring the progress status when the saving/restoration of the registers is resumed.

Abstract: A system including input circuitry for receiving from one of a plurality of sources at least one packet stream including a plurality of packets for providing audio, video, private data and/or associated information; at least one output for outputting at least one packet of the at least one packet stream to circuitry arranged to provide an output stream; wherein the system is arranged to provide a tag indicative of the source, the tag being associated with the at least one packet.