Abstract: A communication network such as a cellular network or a WLAN includes a set of user terminals. Within the communication network, a system dynamically controls spectrum usage. The system includes a functionality sensor for sensing spectrum usage within the area covered by the communication network, and a policy server for producing, as a function of the sensed spectrum usage, spectrum usage policies for the communication network. A broadcasting arrangement broadcasts the spectrum usage policies to the user terminals. The system is applicable to cognitive radio systems.
Abstract: A process for packaging a plurality of micro-components made on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a cover plate; depositing a metal layer on a face of the cover plate or on a face of the wafer; covering the wafer with the cover plate; applying a contact pressure equal to at least one bar onto the cover plate and onto the wafer; and heating the metal layer during pressing until a seal is obtained, each cavity thus being provided with a sealing area and being closed by a part of the cover plate and/or its metal layer.
Type:
Grant
Filed:
November 28, 2005
Date of Patent:
August 16, 2011
Assignee:
STMicroelectronics, S.A.
Inventors:
Guillaume Bouche, Bernard Andre, Nicolas Sillon
Abstract: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.
Abstract: A motion estimation method and device are provided for processing images to be inserted, between a preceding original image and a following original image, into a sequence of images. Each image is divided into pixel blocks associated with motion vectors. For a current block of an image being processed, motion vectors associated with blocks of the image being processed and/or associated with blocks of a processed image are selected. Candidate vectors are generated from selected motion vectors. An error is calculated for each candidate vector. A penalty is determined for a subset of candidate vectors on the basis of the values of the pixels of the pixel block in the preceding original image from which the candidate motion vector points to the current block and/or on the basis of the values of the pixels of the pixel block in the following original image to which the candidate motion vector points from the current block.
Abstract: A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element of the functional circuit. The adjustable circuit also includes a limiter circuit to limit the voltage between the power supply potential and the reference potential to an adjustable limiting voltage, and a circuit to adjust the limiting voltage. After adjusting a parameter of the functional circuit, the limiting voltage of the limiter circuit is adjusted.
Abstract: An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.
Abstract: Embodiments of the present disclosure provide a system and method for remotely accessing media content. The method includes receiving authentication information originating from a communication device associated with a user. Media content that is stored on a media storage device associated with the user is also received. Digital rights management software is applied to the media content, and the received media content is communicated to the communication device.
Abstract: A method processes a signal by storing a template sequence composed of a number N of consecutive digital samples of the signal; calculating a sequence of extended sums that includes, for each digital sample, an extended sum of absolute values of differences between N most recent digital samples and the samples of the template sequence; detecting minima of the sequence of extended sums; and estimating a period of the signal as a time interval between two consecutive minima of the sequence of extended sums. The method also estimates the noise level of the signal as a ratio between most recently-detected minimum and maximum of said sequence of extended sums. The method also generates a reduced-noise replica of the signal as a weighted average of the template sequence and of the current samples of the signal processed between two consecutive minima of said extended sum, the weighted average being calculated using weights based on the estimated noise level.
Type:
Application
Filed:
January 26, 2011
Publication date:
August 11, 2011
Applicant:
STMicroelectronics S.r.l.
Inventors:
Andrea Lorenzo Vitali, Alexandra Gogonea
Abstract: An integrated magnetic sensor formed in a body including a substrate of semiconductor material, which integrates a Hall cell. A trench is formed in the body, for example, on the back of the substrate, and is delimited by lateral surface portions that extend in a direction transverse to the main face of the body. The trench has a depth in a direction perpendicular to the main face that is much greater than its width in a direction parallel to the main face of the body, between the lateral surface portions. A concentrator made of ferromagnetic material is formed within the trench and is constituted by two ferromagnetic regions, which are set at a distance apart from one another and extend along the lateral surface portions of the trench towards the first Hall cell.
Type:
Application
Filed:
February 4, 2011
Publication date:
August 11, 2011
Applicant:
STMicroelectronics S.r.I.
Inventors:
Dario Paci, Caterina Riva, Marco Morelli
Abstract: A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.
Type:
Grant
Filed:
January 26, 2007
Date of Patent:
August 9, 2011
Assignee:
STMicroelectronics (Crolles 2) SAS
Inventors:
Romain Wacquez, Philippe Coronel, Damien Lenoble, Robin Cerutti, Thomas Skotnicki
Abstract: A power supply circuit and a transponder having a circuit for rectifying an A.C. voltage and two power storage elements, the rectifying circuit providing a rectified voltage to at least one of the storage elements and an output voltage being provided by at least one of the storage elements, and at least one switching element for switching the circuit operation between a state of provision of a relatively high voltage and a state of provision of a relatively low voltage, the second state configuring the rectifying circuit in halfwave operation.
Abstract: An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.
Abstract: A methodology for efficiently copying data is presented. An internal controller RAM is multiplexed between storing existing RAM data such as look up table data) and storing copy back data with respect to a flash memory. The data in the controller RAM is temporarily stored in a free space of the flash memory. The data of the flash memory, which is to be copied, is read from a source page and is stored in the free space of the controller RAM, and from there, the data is written to a destination block of the flash memory. After completion of the copy back operation, the data of the controller RAM that was moved to the free space is retrieved for storage back in the controller RAM.
Abstract: An error correction device is provided. Such error correction device may make use of an error correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 21.
Type:
Grant
Filed:
May 19, 2006
Date of Patent:
August 9, 2011
Assignee:
STMicroelectronics S.r.l.
Inventors:
Antonio Griseta, Antonio Lonigro, Angelo Mazzone
Abstract: A thin wafer comprising through holes filled at least partially with conductive carbon nanotubes generally oriented transversally to the wafer. A fuel cell comprising, in a thin wafer, a through hole filled with an electrolyte surrounded with barriers of carbon nanotubes generally oriented transversally to the wafer.
Abstract: A system is provided for modeling an integrated circuit including at least one insulated-gate field-effect transistor. The system includes generator means for defining a parameter representing mechanical stresses applied to the active area of the transistor, and processing means for determining at least one of the electrical parameters of the transistor based at least partially on the stress parameter. Also provided is a method of modeling an integrated circuit including at least one insulated-gate field-effect transistor, and a method of producing an integrated circuit including at least one insulated-gate field-effect transistor.
Abstract: A memory device is a provided that includes memory cells situated at the intersection of lines and columns, and a dummy path including a first dummy column having two bit lines to which there are connected dummy memory cells, and a circuit adapted to select at least one of the dummy memory cells to discharge one of the dummy bit lines. The dummy path also includes at least one second dummy column adapted to generate a dummy leakage current (representing a leakage current of a column of the memory device selected in read mode), and a circuit adapted to copy the dummy leakage current to the one dummy bit line, so that the discharge of the one dummy bit line also depends on the dummy leakage current.
Abstract: A position sensing apparatus and method, motion control system, and integrated circuit are provided that include a plurality of sensors and a tracking processor. The plurality of sensors includes a linear array of sensors that sense a plurality of features of an object. A spacing between two of the plurality of sensors is substantially smaller than a spacing between two of the plurality of features. The tracking processor samples signals from the sensors, compares the samples to previous samples and calculates a position of the object. The plurality of sensors may include a second linear array of sensors. Centers of the sensors of the second linear array may be offset from centers of the sensors of the first linear array along a longitudinal axis of the plurality of sensors.
Abstract: An error correction device is provided. Such error correction device may make use of an error-correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 22.
Abstract: A device comprising a chamber in which a hydrogen-air or methanol-air type fuel cell is arranged, the chamber including an upper wall in which an opening is formed, a lower wall on which the cell is arranged so that the surface of exposure to air of the cell faces the upper wall, and a fan arranged in the opening.
Type:
Application
Filed:
January 28, 2011
Publication date:
August 4, 2011
Applicants:
STMicroelectronics (Tours) SAS, Commissariat à l'Energie Atomique