Abstract: Method and devices are provided for processing an image in which a row of pixels with associated light intensity values successively alternates with a row of pixels to which values are to be associated. In each current row of pixels with associated values, pixels are selected which satisfy a selection rule based on the values for the pixels in the current row with associated values and on the values from the previous and/or the next row with associated values, and segments of pixels are detected. In this manner a set of segments is obtained relative to the image being processed, from which a graph of segments is created by linking the segments according to a linking rule. Then the respective values to be associated with at least some of the pixels in the rows to be assigned values are determined by interpolation from segments in the graph which form a path in the graph.

Abstract: A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract: A plurality of planar electrodes (5) in a microchannel (4) is used for separation, lysis and PCR in a chip (10). Cells from a sample are brought to the electrodes (5). Depending on sample properties, phase pattern, frequency and voltage of the electrodes and flow velocity are chosen to trap target cells (16) using DEP, whereas the majority of unwanted cells (17) flushes through. After separation the target cell (16) are lysed while still trapped. Lysis is carried out by applying RF pulses and/or thermally so as to change the dielectric properties of the trapped cells. After lysis, the target cells (16) are amplified within the microchannel (4), so as to obtain separation, lysis and PCR on same chip (1).

Abstract: A graphic system includes a pipelined graphic engine for generating image frames for display. The pipelined graphic engine includes a geometric processing stage for performing motion extraction, and a rendering stage for generating full image frames at a first frame rate for display at a second frame rate. The second frame rate is higher than the first frame rate. A motion encoder stage receives motion information from the geometric processing stage, and produces an interpolated frame signal representative of interpolated frames. A motion compensation stage receives the interpolated frame signal from the motion encoder stage, and the full image frames from the rendering stage for generating the interpolated frames. A preferred application is in graphic systems that operate in association with smart displays through a wireless connection, such as in mobile phones.

Abstract: Digital signals, such as image/video signals are converted between a first format and a second format by using Multiple Description Coding, whereby the second format conveys multiple descriptions (D1 to D4; D1? to D4?) of the digital signals. In combination with MD coding, the signals are jointly subject to an error concealment process. Preferably, the error concealment process takes place in converting said digital signals from the second format conveying multiple descriptions to the first format.

Abstract: A power converter having a noise component and a modulator configured to vary a frequency of the noise component of the power converter on the basis of a digital signal to be transmitted.

Abstract: The pointing device is used in connection with a computer system, and has a sensor for sensing data representing a displacement information in at least two spatial coordinates. The device is capable of toggling between a first and a second mode of operation, and also adjusting the displacement information referring to a first of the two spatial coordinates (i.e. first displacement information) in view of a second of the two spatial coordinates (i.e. second displacement information) when the second mode of operation is activated.

Abstract: An acceleration sensor includes a semiconductor substrate, a first layer formed on the substrate, a first aperture within the first layer, and a beam coupled at a first end to the substrate and suspended above the first layer for a portion of the length thereof. The beam includes a first boss coupled to a lower surface thereof and suspended within the first aperture, and a second boss coupled to an upper surface of the second end of the beam. A second layer is positioned on the first layer over the beam and includes a second aperture within which the second boss is suspended by the beam. Contact surfaces are positioned within the apertures such that acceleration of the substrate exceeding a selected threshold in either direction along a selected axis will cause the beam to flex counter to the direction of acceleration and make contact through one of the bosses with one of the contact surfaces.

Abstract: A microreactor includes a shell structure (2, 3), having a bottom wall (2) and a peripheral wall (3); a layer (5), accommodated in the shell structure (2, 3) and having cavities (9, 10) formed therein, the cavities being accessible form outside the shell structure (2, 3); reagents (17), arranged between the bottom wall (2) and the layer (5), at locations corresponding to the cavities (9, 10). The layer (5) is made of a meltable material that is solid at room temperature, has a melting point (TMP) lower than a maximum operative temperature (TMAX) required by reactions performable through the microreactor (1) and is not miscible with water. The melting point (TMP) may be between 50° C. and 70° C. In one embodiment, the melting point (TMP) is lower than a minimum operative temperature (TMIN) required by reactions performable through the microreactor (1).

Abstract: An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source and drain regions covered with a metal silicide layer and at least one track of a resistive layer at least partially surrounding the MOS transistor, and adapted to pass a heating current such that the metal of said metal silicide diffuses across drain and/or source junctions.

Abstract: An integrated circuit protected against electrostatic discharges, including input/output pads and first and second power supply rails, and: a thyristor forward-connected between each input/output pad and the second rail, each thyristor including, between its anode gate and its anode, a resistor; between each thyristor and the first rail, a diode having its anode connected to the anode gate of the thyristor and having its cathode connected to the first rail via a resistor for adjusting the triggering; and a triggering device capable of conducting a current between the first and second rails when a positive overvoltage occurs between these rails.

Abstract: An image sensor having a number of pixel zones delimited by isolation trenches, each pixel zone including a photodiode; a transfer gate associated with each of the pixel zones and arranged to transfer charge from the photodiode to a sensing node; and a read circuit for reading a voltage at one of the sensing nodes, the read circuitry including a number of transistors of which at least one is positioned at least partially over a pixel zone of the pixel zones.

Abstract: An image sensor including a plurality of pixels each including a charge collection region including an N-type region bounded by P-type regions and having an overlying P-type layer; and an insulated gate electrode positioned over the P-type layer and arranged to receive a gate voltage for conveying charges stored in the charge collection region through the P-type layer.

Abstract: A clamshell device having a dual accelerometer detector includes a first keyboard portion including a first accelerometer, a second display portion including a second accelerometer, a hinge for coupling the first portion to the second portion, and circuitry coupled to the first and second accelerometers for providing an output signal in response to the position of the first and second portions of the clamshell device. The output signal is provided to indicate a shutdown or standby mode, tablet operation mode, a partially shut or power savings mode, a normal operating mode, or an unsafe operating mode.

Abstract: The appearance of image details can be preserved and/or enhanced by applying contrast adaptive gain to the high spatial frequency component of the luminance information. The image details in bright and/or dark regions can be further boosted by applying a local mean adaptive gain. The contrast transfer mapping curve for luminance contrast enhancement can be re-scaled to account for the applied gain. The re-scaling may be performed from frame to frame of displayed video. The re-scaling may be temporally controlled for subsequent frames to make the re-scaling change gradually to prevent flickering.

Abstract: A demodulator is provided for demodulating an amplitude-modulated input signal defined by a carrier signal having a carrier frequency modulated by a modulating signal, the demodulator including an amplifier stage having a gain and structured to receive the amplitude-modulated input signal, and a gain control stage coupled to the amplifier stage and configured to vary the gain of the amplifier stage according to the carrier frequency of the carrier signal.

Abstract: An inductor formed in a stacking of insulating layers. The inductor comprises first and second access terminals, at least first and second interlaced loops on a first level, and at least third and fourth interlaced loops on a second level distinct from the first level. The third loop is the symmetrical of the first loop with respect to a plane. The fourth loop is the symmetrical of the second loop with respect to said plane. The internal ends of the first and second loops are connected to the internal ends of the third and fourth loops. The external ends of the first and third loops are connected to the first and second access terminals. The external ends of the second and fourth loops are interconnected.

Abstract: A corrector circuit for correcting second harmonic distortions is provided. The corrector circuit includes a transconductance circuit having an input transconductance with a transresistance load for receiving a distorted voltage signal having a second harmonic component. The transconductance circuit is adapted to generate a corrected voltage signal having the second harmonic component that is reduced from the distorted voltage signal as a function of the input transconductance. The corrector circuit further includes biasing means for providing a biasing current to the transconductance circuit (with the input transconductance that depends on the biasing current). The biasing means includes means for providing a fixed component of the biasing current, means for providing a variable component of the biasing current (being a function of the distorted voltage signal according to a proportionality coefficient) and means for programming the proportionality coefficient.

Abstract: A method for managing the access to a memory space shareable by several users, by using passwords, comprises: defining a maximum number of passwords, providing a password storage zone, dividing the shareable memory space into a plurality of blocks greater in number than the maximum number of passwords, providing in each block a parameterization field for parameterizing the protection of the block, providing in each parameterization field a binary index smaller in size than a password and designating a password assigned to the protection of the block, and allocating, to each block, access rights requiring a password to be presented corresponding to the password designated by the index present in the block parameterization field. Application is provided particularly but not exclusively to multi-user integrated circuits.