Abstract: An integrated circuit includes non-volatile storage configured to secretly store a digital word, the value of which forms an identification code. The integrated circuit also includes control circuitry configured to receive the digital word and to generate transient electrical currents or transient voltages, the characteristics of which depend on the value of the digital word. There is an electrically conductive network configured to be passed through by the electrical currents or receive the transient voltages so as to generate an electromagnetic field that identifies the integrated circuit.

Abstract: A threshold comparator with hysteresis includes a comparator circuit, having a first input, for receiving an input voltage, a second input, and an output, which supplies an output voltage having a first value and a second value. A current generator, controlled by the output voltage, supplies a current to the first input in the presence selectively of one between the first value and second value of the output voltage. A selector circuit connects the second input of the comparator circuit to a first reference voltage source, which supplies a first reference voltage, in response to first edges of the output voltage, and to a second reference voltage source, which supplies a second reference voltage, in response to second edges of the output voltage, opposite to the first edges.

Abstract: An electronic amplifier for driving a capacitive load may include first and second differential input terminals to receive an input signal, and first and second differential output terminals to provide a differential output signal. The amplifier may further include a first operational device having first and second differential inputs connected to the first and second differential input terminals, respectively, and an output connected to the first differential output terminal, and a second operational device having first and second differential inputs connected to the first and second differential input terminals, respectively, and an output connected to the second differential output terminal. The first and second operational devices may be operatively configured so that both the first and the second output terminals are at a same reference potential during periods in which a module of differential output signal amplitude decrease.

Abstract: Method for improving the symmetry of the differential output signals of an integrated transformer of the symmetric-asymmetric type comprising an inductive primary circuit and an inductive secondary circuit, characterized in that the capacitive coupling between the primary and secondary circuits is reduced.

Abstract: In a method for making an on-chip interconnect for conveying between a set of initiators and a set of targets in which traffic is organized in classes of service, priority values representing the classes of service are associated with the traffic. The method further includes propagating the priority values towards the points of the network where an arbitration is performed between two classes of service of the traffic, and providing arbitration as a function of the priority values.

Abstract: A memory card and a communication method between a memory card and a host unit are disclosed. High throughput of data between the memory card and the host unit is guaranteed by providing a communication interface between the memory card and the host unit including a first communication interface between a memory unit of the memory card and a control unit of the memory card and a second communication interface between the control unit of the memory card and the host unit.

Abstract: A DC-DC converter includes a power switching device and a mode control logic circuit to control the power switching device and generate an ON-pulse. A flip-flop is configured to be set by the mode control logic circuit. A current mode comparator is configured to reset the flip-flop and to compare a signal based upon current flowing through the power switching device with a signal based upon an output voltage of the dual mode flyback DC-DC converter. A transformer is driven by the current mode comparator.

Abstract: An oscillator comprises an inverter, with a resonator connected between an input and an output of the inverter. A transistor external to the inverter is connected in a current mirror mode with a transistor of the inverter so that the inverter's transistor copies the current of the external transistor. The external transistor has its drain terminal connected to the gate terminals of the inverter's transistor and of the external transistor. A current source is connected to the gate terminal of the inverter's transistor, and a switch is connected between the drain and gate terminals of the external transistor. Circuitry controls the switch so as to open the connection between the drain and gate terminals of the external transistor at the beginning of a start-up phase of the oscillator.

Abstract: A method is for choosing a mode out of a set of functioning modes of an integrated circuit (IC) device powered from different supply voltages from respective supply nodes. The IC device may include a mode pin for determining a functioning mode of the device, an internal control circuit coupled to the supply nodes and to the mode pin for sensing an electrical value on the mode pin and to start the IC device in a respective functioning mode depending on the supply node that is powered first. The method may include identifying the different supply voltage that first exceeds a threshold voltage, when the internal control circuit is powered, sensing the electrical value on the mode pin, and powering circuits of the IC device from the different supply voltage that first exceeded the threshold voltage and starting the device in a functioning mode determined by a value of the electrical value sensed on the mode pin and by the different supply voltage that first exceeded the voltage threshold.

Abstract: A circuit for a voltage controlled oscillator has a bridge structure including two cross-coupled N-type transistors and two cross-coupled P-type transistors. A current mirror is coupled to the two N-type cross-coupled transistors and configured to generate a bias current. An LC resonator is coupled in parallel between the two cross-coupled N-type transistors and the two P-type cross-coupled transistors. The LC resonator includes two pairs of differential inductors mutually coupled by a mutual inductance coefficient, each pair comprising a first inductor arranged on a respective branch of an external loop, and a second inductor arranged on a respective branch of an internal loop. A first varactor is coupled to a common node and a first branch of the internal loop. A second varactor is coupled to the common node and the second branch of the internal loop.

Abstract: Composite materials having conductive properties are described for use in testing circuits and in manufacturing electrical switches. The composite materials described, when in an unstressed state, generally behave as insulators. However, when sufficient mechanical pressure is applied to portions of the composite materials, the portions to which the mechanical pressure is applied become increasingly conductive. Methods for testing a PCB using composite material switches are also disclosed. A sheet that includes a composite material may be used to test electrical functionality of various regions on a PCB by way of local pressure application. The sheet may be easily applied to and removed from the PCB. Additionally, in forming an electrical switch, a voltage applied to one or more actuating elements may be used to provide mechanical pressure to a composite material that is disposed between two conductive members.

Abstract: A time-domain method of adaptively levelling the loudness of a digital audio signal is proposed. It selects a proper frequency weighting curve to relate the volume level to the human auditory system. The audio signal is segmented into frames of a suitable duration for content analysis. Each frame is classified to one of several predefined states and events of perceptual interest is detected. Four quantities are updated each frame according to the classified state and detected event to keep track of the signal. One quantity measures the long-term loudness and is the main criterion for state classification of a frame. The second quantity is the short-term loudness that is mainly used for deriving the target gain. The third quantity measures the low-level loudness when the signal is deemed to not contain important content, giving a reasonable estimate of noise floor. A fourth quantity measures the peak loudness level that is used to simulate the temporal masking effect.

Abstract: An electronic integrated device may include a signal generation stage arranged to generate a first signal representative of an under voltage lockout logic signal. The signal generation stage may include a voltage divider block arranged to provide an internal reference voltage signal to a bandgap core group based upon a reference signal. The bandgap core group may generate the first signal based upon the internal reference voltage signal. The bandgap core group may further include a first generation module arranged to generate a output regulated reference voltage signal based upon the internal reference voltage signal, and a second generation module arranged to generate the first signal based upon the internal reference voltage signal and a driving signal obtained by a preliminary processing of the internal reference voltage signal by a bandgap core module included within the band gap core group.

Abstract: A method for fabricating electrical bonding pads on the electrical contact areas of a wafer includes producing first blocks made of a solder material, producing second blocks made of a solder material on these first blocks, and passing the blocks through an oven so as to shape the blocks into approximately domed electrical bonding pads.

Abstract: A method of controlling a pulse width modulated (PWM) voltage regulator including a control circuit of a power stage, and a circuit configured to determine a duration of charge phases and further configured to receive a charge signal and to generate a logic command may include controlling, using the control circuit, switches of the power stage as a function of the logic command at an end of a charge phase and at a start of a discharge phase of an output capacitance. The method may also include generating the charge signal to be one of enabled and disabled during charge phases and another of enabled and disabled during discharge phases, and delaying, at each PWM cycle, the logic command with respect to a previous PWM cycle to compensate at least one of a phase and a frequency difference between each PWM cycle and a reference clock signal.

Abstract: Embodiments related to an undervoltage detector are described and depicted. An undervoltage detector is formed to detect a low input bias voltage with a voltage divider network including first and second series circuits of semiconductor devices coupled to terminals of the input bias voltage source, and a resistor voltage divider including first and second voltage divider resistors coupled in series with the first and second series circuits. A ratio representing the numbers of semiconductor devices in the series circuits is substantially equal to a ratio of resistances in the resistor voltage divider. The equality of the ratios may be corrected by the presence of other resistances in the undervoltage detector. The semiconductor devices are each coupled in a diode configuration. The first series circuit is coupled to a current mirror to provide a bias current for a comparator that produces an output signal for the undervoltage detector.

Abstract: An input device may include an image sensor having an imaging surface comprising an array of pixels, and an optical waveguide layer carried by the imaging surface and having an exposed user surface and a first refractive index associated therewith. The input device may also include a substrate between the optical waveguide layer and the image sensor and having a second refractive index associated therewith that is lower than first refractive index. A collimation layer may be between the image sensor and the substrate. A light source may be configured to transmit light into the optical waveguide so that the light therein undergoes a total internal reflection. The optical waveguide may be being adjacent the imaging surface so that an object brought into contact with the exposed user surface disturbs the total internal reflection results in an image pattern on the imaging surface.

Abstract: A method for transmitting at least a synchronization and a data signal on a single-wire bus between a master device and at least one slave device, wherein a first transmission channel from the master device to the slave device modulates the periodic pulse width between a first level and second level of a same sign voltage relative to a reference potential, and a second transmission channel amplitude modulates at least one of the voltage levels between the level and at least one third level different from the two others and from the reference potential.

Abstract: A method includes growing a first oxide region concurrently with a second oxide region in a substrate and forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region. The method also includes removing the first oxide region to form a chamber, forming a first MOS transistor adjacent the second oxide region, and forming a second MOS transistor separated from the first MOS transistor by the second oxide region.

Abstract: A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates.