Patents Assigned to STMicroelectronics
  • Publication number: 20110129040
    Abstract: A method of estimating log-likelihood ratios for first and second streams of samples of a received S-FSK signal demodulated using first and second carriers includes estimating channel and noise parameters associated with first and second transmitted values for the first and second streams of samples obtained from the received S-FSK modulated signal. Current signal-to-noise ratios are estimated for current samples of the first and second streams of samples obtained from the received S-FSK modulated signal using the channel and noise parameters. The estimated current signal-to-noise ratios are compared with values of a discrete ordered set and respective pairs of consecutive values of the discrete ordered set between which the estimated current signal-to-noise ratios are comprised are identified. Log-likelihood ratios are estimated for the current samples of the first and second streams.
    Type: Application
    Filed: November 24, 2010
    Publication date: June 2, 2011
    Applicant: STMicroelectronics S.r.I.
    Inventors: Daniele VERONESI, Lorenzo Guerrieri
  • Publication number: 20110128419
    Abstract: A method and system is for limiting the x-droop effect in the digital image captured with solid state image sensors with a correction mechanism which instead of using only correction values from the same column to which the correction is applied, also takes the neighboring pixels into account to provide an averaged value to aid in the reduction of temporal and fixed noise contributions associated with the readout of a single pixel.
    Type: Application
    Filed: November 1, 2010
    Publication date: June 2, 2011
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventor: John Kevin MOORE
  • Publication number: 20110129967
    Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device connected in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal connected to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, connected between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal connected to the control terminal; and a Zener diode, connected between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.
    Type: Application
    Filed: January 31, 2011
    Publication date: June 2, 2011
    Applicant: STMicroelectronics S.r.I.
    Inventors: Cesare RONSISVALLE, Vincenzo ENEA
  • Publication number: 20110129024
    Abstract: In an embodiment, a channel estimator includes first and second stages. The first stage is operable to generate a respective one-dimensional array of first channel-estimation coefficients for each communication path of a communication channel, and the second stage is operable to generate a multi-dimensional array of second channel-estimation coefficients in response to the first channel-estimation coefficients. For example, such a channel estimator may estimate the response of a channel over which propagates an orthogonal-frequency-division-multiplexed (OFDM) signal that suffers from inter-carrier interference (ICI) due to Doppler spread. Such a channel estimator may estimate the channel response more efficiently, and with a simpler algorithm, than conventional channel estimators.
    Type: Application
    Filed: December 8, 2010
    Publication date: June 2, 2011
    Applicants: STMicroelectronics, Inc., STMicroelectronics Asia Pacific PTE, Ltd.
    Inventors: Muralidhar KARTHIK, George A. VLANTIS
  • Publication number: 20110131189
    Abstract: A method for managing a queue, such as for example a FIFO queue, and executing a look-ahead function on the data contained in the queue includes associating to the data in the queue respective state variables (C1, C2, . . . CK), the value of each of which represents the number of times a datum is present in the queue. The look-ahead function is then executed on the respective state variables, preferentially using a number of state variables (C1, C2, . . . CK) equal to the number of different values that may be assumed by the data in the queue. The look-ahead function can involve identification of the presence of a given datum in the queue and is, in that case, executed by verifying whether among the state variables (C1, C2, . . . CK) there exists a corresponding state variable with non-nil value.
    Type: Application
    Filed: November 22, 2010
    Publication date: June 2, 2011
    Applicant: STMicroelectronics S.r.I.
    Inventors: Daniele MANGANO, Giovanni Strano, Salvatore Pisasale
  • Publication number: 20110130177
    Abstract: A camera module may include a substrate, and an image sensor mounted on the substrate. The camera module may also include a housing, and an electromagnetic interference (EMI) shield provided around the image sensor and within the module. The camera module may be particularly suited for use in a mobile telephone, for example.
    Type: Application
    Filed: November 29, 2010
    Publication date: June 2, 2011
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Publication number: 20110131467
    Abstract: Systems and methods for encoding and decoding at least one logical block address in a low density parity check (LDPC) are disclosed. These systems and methods can include selecting a LDPC Code matrix and a parity check matrix wherein the LDPC Code matrix and the parity check matrix have an orthogonal relationship. These systems and methods may further include encoding a data element using at least some of the LBA bits in the parity bits in a LDPC codeword creating a parity vector using the at least some of the LBA bits in the LDPC codeword.
    Type: Application
    Filed: August 5, 2010
    Publication date: June 2, 2011
    Applicant: STMicroelectronics, Inc.
    Inventor: Anthony Weathers
  • Publication number: 20110128420
    Abstract: Repeated Fixed Pattern Noise (FPN) in solid state image sensors for a digitally encoded image captured with a sensor is corrected by exploits the periodicity of FPN pattern. In this way FPN is compensated by using a repeating pattern that is associated with repeating blocks of layout.
    Type: Application
    Filed: November 12, 2010
    Publication date: June 2, 2011
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventor: John Kevin Moore
  • Publication number: 20110128070
    Abstract: A charge pump having a supply terminal, for receiving a supply voltage, and an output terminal, for supplying an output voltage. The charge pump has a control block including a comparator having a first comparison input, for receiving the supply voltage, a second comparison input, for receiving the output voltage, and a comparison output, for generating a pump-switch-off signal depending upon a comparison between the input voltage and the output voltage; and a switch controlled in switching off by the pump-switch-off signal and configured for switching off the charge pump circuit. The control block has an activation input for receiving an activation signal that has a plurality of pulses and repeatedly activates the comparator-circuit block.
    Type: Application
    Filed: November 29, 2010
    Publication date: June 2, 2011
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.I.
    Inventors: Santi Nunzio Antonino Pagano, Francesco La Rosa, Alfredo Signorello
  • Patent number: 7952458
    Abstract: A mode-switching transformer with a 1-to-4 impedance ratio having a first planar winding formed in a first conductive level from a first differential mode terminal outside of the winding; a second planar winding formed in a second conductive level from a second differential mode terminal outside of the winding; a via of interconnection of the central ends of the first and second windings intended to be connected to ground; and at least one third planar winding in one of the two conductive levels, interdigited with the first or the second winding from a first common-mode terminal outside of the winding, the internal end of the third winding being connected to the via for direct grounding.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Hilal Ezzeddine
  • Patent number: 7952104
    Abstract: A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Salvatore Leonardi, Claudia Caligiore
  • Patent number: 7953994
    Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Satinder Singh Malhi, Arant Agrawal
  • Patent number: 7954017
    Abstract: A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Amit Kashyap, Prashant Dubey, Akhil Garg
  • Patent number: 7953366
    Abstract: A receiver that can receive several initial signals modulated in a same initial frequency band and/or distinct initial frequency bands and generate a signal modulated in a transmission band to be transmitted on a coaxial cable, comprising a selector that can select several signals from among the received signals; for each selected signal, a mixer capable of transforming the selected signal into a signal at least partly in the transmission band, and a filter capable of extracting from the transformed signal a signal associated with a portion of the transmission band from among several at least partly distinct portions of the transmission band; and means for forming the signal modulated in the transmission band from signals associated with the transmission band portions.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics, SA
    Inventor: Jean-Yves Couet
  • Patent number: 7953379
    Abstract: A calibration method for reducing modulation errors in a telecommunication transmitter apparatus includes providing a plurality of pairs of test signals; the test signals of each pair are substantially in quadrature to each other, and the pairs of test signals are at least in part different with all the pairs of test signals that have a substantially equal energy. A plurality of modulated signals are generated, with each modulated signal that is generated by modulating a corresponding pair of test signals. A plurality of transformed signals are calculated, each one corresponding to the square of a corresponding modulated signal in the frequency domain. A plurality of partial error indicators are calculated, each one as a function of the modulus of a corresponding transformed signal. The partial error indicators are indicative of the modulation errors associated with the modulated signals.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventor: Angelo Poloni
  • Patent number: 7954153
    Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics SA
    Inventors: Frédéric Bancel, Nicolas Berard
  • Patent number: 7952173
    Abstract: A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Danilo Mascolo, Gianfranco Cerofolini, Gianguido Rizzotto
  • Patent number: 7953286
    Abstract: In a process for enhancing contrast of an image having pixels in different brightness intensities, a histogram in discrete bins is generated. Each bin represents a pixel population of at least one pixel brightness intensity. A peak and a peak region of the histogram is then identified, wherein the peak region is a range of discrete bins around the peak. An average pixel population within the peak region is computed, and the pixel populations of the discrete bins within the peak region that exceeds the average pixel population are distributed. A transfer curve for mapping onto the image is then generated. The process can be used in an image processor for enhancing contrast of an image having pixel. Still further, a display having a receiver and a screen can include the foregoing image processor.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Patricia Wei Yin Chiang, Yau Wai Hui
  • Patent number: 7952411
    Abstract: A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay element, the control signal selectively being in a first logic state or a second logic state wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to the
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Robert G. Warren
  • Publication number: 20110124157
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 26, 2011
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau