Abstract: In an embodiment, a channel estimator includes first and second stages. The first stage is operable to generate a respective one-dimensional array of first channel-estimation coefficients for each communication path of a communication channel, and the second stage is operable to generate a multi-dimensional array of second channel-estimation coefficients in response to the first channel-estimation coefficients. For example, such a channel estimator may estimate the response of a channel over which propagates an orthogonal-frequency-division-multiplexed (OFDM) signal that suffers from inter-carrier interference (ICI) due to Doppler spread. Such a channel estimator may estimate the channel response more efficiently, and with a simpler algorithm, than conventional channel estimators.

Abstract: A method and a device for monitoring a digital signal, wherein a first P-channel MOS transistor is placed in degradation conditions of negative bias temperature instability type during periods when the signal to be monitored is in a first state; a first quantity representative of the saturation current of the first transistor is measured when the signal to be monitored switches to a second state; and a detection signal is switched when this first quantity exceeds a threshold.

Abstract: Disk drive spindle jitter is comprised of electrical noise, error due to pair pole asymmetry, and random disk speed variances. Error caused by pair pole asymmetry can be identified and compensated for by detecting over a single rotation of a rotor a plurality of zero cross signals. These signals can be statistically analyzed over a period of a plurality of revolutions of the rotor so as to identify the systematic error caused by pair poles. Once identified, this pair pole error can be used to modify zero cross signals and/or modify commutation signal driving the disk so as to arrive at a more accurate determination of disk speed and to precisely control the speed of the disk.

Abstract: A method of estimating log-likelihood ratios for first and second streams of samples of a received S-FSK signal demodulated using first and second carriers includes estimating channel and noise parameters associated with first and second transmitted values for the first and second streams of samples obtained from the received S-FSK modulated signal. Current signal-to-noise ratios are estimated for current samples of the first and second streams of samples obtained from the received S-FSK modulated signal using the channel and noise parameters. The estimated current signal-to-noise ratios are compared with values of a discrete ordered set and respective pairs of consecutive values of the discrete ordered set between which the estimated current signal-to-noise ratios are comprised are identified. Log-likelihood ratios are estimated for the current samples of the first and second streams.

Abstract: A camera module may include a substrate, and an image sensor mounted on the substrate. The camera module may also include a housing, and an electromagnetic interference (EMI) shield provided around the image sensor and within the module. The camera module may be particularly suited for use in a mobile telephone, for example.

Abstract: A charge pump having a supply terminal, for receiving a supply voltage, and an output terminal, for supplying an output voltage. The charge pump has a control block including a comparator having a first comparison input, for receiving the supply voltage, a second comparison input, for receiving the output voltage, and a comparison output, for generating a pump-switch-off signal depending upon a comparison between the input voltage and the output voltage; and a switch controlled in switching off by the pump-switch-off signal and configured for switching off the charge pump circuit. The control block has an activation input for receiving an activation signal that has a plurality of pulses and repeatedly activates the comparator-circuit block.

Abstract: Systems and methods for encoding and decoding at least one logical block address in a low density parity check (LDPC) are disclosed. These systems and methods can include selecting a LDPC Code matrix and a parity check matrix wherein the LDPC Code matrix and the parity check matrix have an orthogonal relationship. These systems and methods may further include encoding a data element using at least some of the LBA bits in the parity bits in a LDPC codeword creating a parity vector using the at least some of the LBA bits in the LDPC codeword.

Abstract: A method for managing a queue, such as for example a FIFO queue, and executing a look-ahead function on the data contained in the queue includes associating to the data in the queue respective state variables (C1, C2, . . . CK), the value of each of which represents the number of times a datum is present in the queue. The look-ahead function is then executed on the respective state variables, preferentially using a number of state variables (C1, C2, . . . CK) equal to the number of different values that may be assumed by the data in the queue. The look-ahead function can involve identification of the presence of a given datum in the queue and is, in that case, executed by verifying whether among the state variables (C1, C2, . . . CK) there exists a corresponding state variable with non-nil value.

Abstract: Repeated Fixed Pattern Noise (FPN) in solid state image sensors for a digitally encoded image captured with a sensor is corrected by exploits the periodicity of FPN pattern. In this way FPN is compensated by using a repeating pattern that is associated with repeating blocks of layout.

Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.

Abstract: A mode-switching transformer with a 1-to-4 impedance ratio having a first planar winding formed in a first conductive level from a first differential mode terminal outside of the winding; a second planar winding formed in a second conductive level from a second differential mode terminal outside of the winding; a via of interconnection of the central ends of the first and second windings intended to be connected to ground; and at least one third planar winding in one of the two conductive levels, interdigited with the first or the second winding from a first common-mode terminal outside of the winding, the internal end of the third winding being connected to the via for direct grounding.

Abstract: A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.

Abstract: A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.

Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract: A receiver that can receive several initial signals modulated in a same initial frequency band and/or distinct initial frequency bands and generate a signal modulated in a transmission band to be transmitted on a coaxial cable, comprising a selector that can select several signals from among the received signals; for each selected signal, a mixer capable of transforming the selected signal into a signal at least partly in the transmission band, and a filter capable of extracting from the transformed signal a signal associated with a portion of the transmission band from among several at least partly distinct portions of the transmission band; and means for forming the signal modulated in the transmission band from signals associated with the transmission band portions.

Abstract: A calibration method for reducing modulation errors in a telecommunication transmitter apparatus includes providing a plurality of pairs of test signals; the test signals of each pair are substantially in quadrature to each other, and the pairs of test signals are at least in part different with all the pairs of test signals that have a substantially equal energy. A plurality of modulated signals are generated, with each modulated signal that is generated by modulating a corresponding pair of test signals. A plurality of transformed signals are calculated, each one corresponding to the square of a corresponding modulated signal in the frequency domain. A plurality of partial error indicators are calculated, each one as a function of the modulus of a corresponding transformed signal. The partial error indicators are indicative of the modulation errors associated with the modulated signals.

Abstract: In a process for enhancing contrast of an image having pixels in different brightness intensities, a histogram in discrete bins is generated. Each bin represents a pixel population of at least one pixel brightness intensity. A peak and a peak region of the histogram is then identified, wherein the peak region is a range of discrete bins around the peak. An average pixel population within the peak region is computed, and the pixel populations of the discrete bins within the peak region that exceeds the average pixel population are distributed. A transfer curve for mapping onto the image is then generated. The process can be used in an image processor for enhancing contrast of an image having pixel. Still further, a display having a receiver and a screen can include the foregoing image processor.

Abstract: A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.

Abstract: A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay element, the control signal selectively being in a first logic state or a second logic state wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to the

Abstract: A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.