Abstract: A system and method for determining the start position of a motor. According to an embodiment, a voltage pulse signal may be generated across a pair of windings in a motor. A current response signal will be generated and based upon the position of the motor, the response signal will be greater in one pulse signal polarity as opposed to an opposite pulse signal polarity. The response signal may be compared for s specific duration of time or until a specific integration threshold has been reached. Further, the response signal may be converted into a digital signal such that a sigma-delta circuit may smooth out glitches more easily. In this manner, the position of the motor may be determined to within 60 electrical degrees during a startup.

Abstract: An integrated circuit includes a bandgap reference generator and a voltage regulator. The bandgap reference generator includes a first current path, and a first bipolar transistor with an emitter-collector path in the first current path. The voltage regulator includes a second current path, wherein the second current path mirrors the first current path; a resistor configured to receive a current of the second current path; a second bipolar transistor with a base and a collector of the second bipolar transistor being interconnected; and a third bipolar transistor connected in series with the second bipolar transistor and the resistor. A base and a collector of the third bipolar transistor are interconnected.

Abstract: A smart card device includes a card body; and a plurality of card contacts carried by the card body. A smart card chip circuit includes a processor carried by the card body and operably connected to the contacts. At least one memory stores a set of instructions relating to initiating and completing smart card transactions between the smart card device and a smart card host. A biometric circuit is carried by the card body and operable with the processor and used for verifying identity of a user for subsequent smart card device usage. Power is received through a first contact for powering a power circuit for the smart card and a biometric subsystem power circuit receives power through a second contact.

Abstract: A DC-DC converter including: a switch, having a control terminal receiving a control signal, and a conduction terminal supplying a current; a load, coupled to the conduction terminal of the switch and selectively receiving the current; a control circuit, receiving a clock signal and generating the control signal in synchronism with the clock signal; an overcurrent sensor, coupled to the switch so as to monitor an electrical quantity correlated to the current and to output a protection signal in presence of overcurrent; moreover including overcurrent-protection circuitry, receiving the protection signal and the clock signal and generating a disabling signal for the control circuit if delay between an overcurrent detection and the clock signal is shorter than a detection time.

Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Abstract: A method and a circuit for generating a secret quantity based on an identifier of an integrated circuit, including combining a first digital word derived from a physical parameter network with a second word stored in a non-volatile memory element.

Abstract: An image comprises columns and rows of blocks of pixels. In each row and/or column, a series of pairs of blocks of pixels comprise first and second adjacent blocks of pixels, with the second block in a previous pair of blocks corresponding to the first block in a next pair of blocks. For at least a part of the pairs of blocks in at least a part of the rows and/or columns of blocks in the image, a method determines an indication of a block boundary between the first and second blocks. The method decides based on the determined indication whether the block boundary is a visible or invisible block boundary. These steps are then repeated for a next pair. If at least one invisible block boundary is present between two visible block boundaries, it is decided that a uniform image distortion zone has been detected.

Abstract: A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed.

Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is connected as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Abstract: A hierarchical row decoder is for a phase-change memory device provided with an array of memory cells organized according to a plurality of array wordlines and array bitlines. The row decoder has a global decoder that addresses first and a second global wordlines according to first address signals; and a local decoder, which is operatively coupled to the global decoder and addresses a respective array wordline according to the value the first and second global wordline and second address signals. The local decoder has a first circuit branch providing, when the first global wordline is addressed, a first current path between the array wordline and a first biasing source during a reading operation; and a second circuit branch providing, when the second global wordline is addressed, a second current path, distinct from the first current path, between the array wordline and a second biasing source during a programming operation.

Abstract: A system is for transmitting data in a network and includes emitter nodes, each including a transmitter for transmitting requests for data transmission. The system may also include a receiver node receiving the data transmission from the emitter nodes and including a first memory for storing data transmitted by each emitter node, a second memory for storing the requests, and a transmitter. The data may be transmitted from the emitter nodes to the receiver node when memory space is available in the first memory to receive data. The transmitter of the receiver node may transmit to each emitter node an acknowledgement message when memory space is available in the first memory to receive at least a portion of the data transmitted. Each emitter node may establish a communication link with the receiver node and transmits the data based upon the acknowledgement message. The communication link may be locked until all data is transmitted.

Abstract: By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide.

Abstract: The image sensor includes an array of pixels, each pixel having a photo-diode, for providing a pixel voltage, an analog-to-digital converter (ADC) operable to convert the pixel voltage to a digital value and a memory for storing the digital value. Read circuitry is included for reading out the digital values from the pixels of the array in a predetermined order. The image sensor may be configured such that a counter incorporates the memory, and the counter may be adapted to operate as a shift register. The counters of two or more pixels may be connected to form one or more chains such that digital values can be read out in a bit-serial manner.

Abstract: An asynchronous set-reset circuit device for testing activity performed by an Automatic Test Patterns Generation tool may include a pair of logic gates having at least two inputs each, and a logic gate structure coupled upstream from the pair of logic gates. The logic gate structure may be for driving one respective input of the pair of logic gates and may have inputs receiving a pair of test command signals. The asynchronous set-reset circuit device may also include a plurality of feedback connections between outputs of the pair of logic gates and respective inputs of the logic gate structure.

Abstract: An interface device having a first and second data terminal configured for the communication of data in duplex mode, with one of the first and second data terminals always assigned to each direction of the communication, the first and second data terminals configurable during operation such that, in a first mode of operation, the first data terminal is configured to send but not to receive data and the second data terminal is configured to receive but not send data, while in a second mode of operation the first data terminal is configured to receive but not to send data and the second data terminal is configured to send but not to receive data.

Abstract: A bit detection event within a read period is characterized by sub-dividing each read period into elementary time intervals. Certain ones of the elementary intervals are selected to for a window and a counting operation for a number of bits detected during the intervals within the window is performed. The elementary time intervals are defined by a difference between a frequency corresponding to the read period and a bit detection timing frequency. The counting result for the intervals in the window over several consecutive read periods is statistically processed. A reduction of an integrated electronic circuit test duration results from limiting the counting operations performed to the selected elementary time intervals.

Abstract: A method and a system for coding digital data represented by source symbols (Si) with an error-correction code. The error-correction code generates parity symbols (Pj) based on, for each parity symbol, several source symbols and at least one parity symbol of preceding rank. At least a part of the source symbols is submitted to at least a first ciphering. The obtained ciphered symbols and the rest of the unciphered source symbols are submitted to the error-correction code.

Abstract: A method for protecting the execution of a main program against possible traps, including, on occurrence of an instruction from the main program, starting a time counter of a given count according to next instructions of the main program, and executing, once the counter has reached its count, at least one instruction of a secondary program from which the result of the main program depends.

Abstract: An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The reference signal is a function of a reference clock signal. The TDC is configured to generate a digital word, the feedback word being a function of the digital word. The ADPLL includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal.

Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.