Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Abstract: A device includes a memory and processing circuitry coupled to the memory. The processing circuitry, in operation: estimates an angular rate of change and determines a rotational versor based on the rotational data; and estimates a gravity vector based on the angular rate of change and the rotational versor. The processing circuitry generates a dynamic gravity vector based on the estimated gravity vector, a correction factor and an estimated error in estimated gravity vector. The processing circuitry estimates a linear acceleration and determines an acceleration versor based on the acceleration data, and determines the correction factor based on the linear acceleration. The processing circuitry estimates the error in the estimated gravity vector based on the acceleration versor.

Abstract: An integrated circuit semiconductor dice has first and second opposed surfaces. First and second electrically conductive patterns extending at the first and second opposed surfaces provide electrical coupling to the semiconductor die. An electrical component, such as a capacitor, having a length transverse to the first and second opposed surfaces of the semiconductor die, extends bridge-like between the first and second opposed surfaces. Opposed electrical contact end terminals of the electrical component are coupled to the first and second electrically conductive patterns. The electrical component is thus electrically coupled to the semiconductor die via the first and second electrically conductive patterns at the first and second opposed surfaces.

Abstract: A non-volatile memory includes current sectors and a substitution sector. The non-volatile memory is controlled to store data into the sectors and to erase data stored in one of the sectors by erasing all the data stored in that sector at once. The current sectors include a first current sector storing at least one first valid data element and a second current sector storing at least one second valid data element. A determination is made that one of the current sectors is to be erased. One sector among the current sectors is selected. Valid data in the selected current sector is then copied into the substitution sector. All data in the selected current sector then erased.

Abstract: In an electronic device, a pulse generator receives an input signal and a clock signal and produces a transmission signal that includes a pulse following each edge of the input signal and of the clock signal. The pulse is low when the input signal is low and high when the input signal is high. A transmitter produces, at its two output nodes, a replica of the transmission signal and the complement of the transmission signal. A galvanic isolation barrier is coupled to the output nodes of the transmitter and produces a differential signal that includes a positive spike at each rising edge of the transmission signal and a negative spike at each falling edge of the transmission signal.

Abstract: The present disclosure is directed to a method of forming a conductive trace in a substrate. A pattern of the trace is formed in the substrate by a laser machining technique. The pattern of the trace is covered by palladium colloid. The palladium colloid is transferred to the patterned substrate by a laser-induced forward transfer (LIFT) technique. The palladium colloid is converted to a palladium plating catalyst layer by a palladium acceleration process. The palladium plating catalyst layer provides a sufficient catalyst to grow a metal seeding layer by an electroless copper deposition technique. In addition, the palladium plating catalyst layer includes portions of tin material which increases adhesion of the metal seeding layer into the substrate. After growing the metal seeding layer, the pattern of the trace is filled by a copper layer through an electrochemical deposition technique.

Abstract: A method is presented for monitoring a tampering state of closed container wherein a first electrically conductive wire extends across a slot between two portions of the closed container. The method includes applying a voltage across the first electrically conductive wire, sensing a voltage at one end of the first electrically conductive wire, and generating a signal indicating the tampering state of the closed container in response to the sensed voltage. The sensed voltage has a first voltage value if the first electrically conductive wire has been severed by tampering, and this tampered state is then reported using near field communication. The near field communication is blocked if it is sensed that the severed first electrically conductive wire has been repaired.

Abstract: A memory array includes memory cells arranged in rows and columns where each row includes a word line connected to memory cells of the row and each column includes a bit line connected to memory cells of the column. Each memory cell stores a bit of weight data for an in-memory computation operation. A row controller circuit coupled to the word lines through drive circuits is configured to simultaneously actuate multiple word lines during the in-memory computation operation. A column processing circuit includes a discharge time sensing circuit for each column that generates an analog signal indicative of a time taken during the in-memory computation operation to discharge the bit line from a precharge voltage to a threshold voltage. The analog signals are converted to digital signal and a computation circuitry performs digital signal processing calculations on the digital signals to generate a decision output for the in-memory computation operation.

Abstract: Electronic device, comprising: a solid body including a Silicon Carbide substrate, and further including an electrical terminal of the electronic device on the substrate; a passivation layer on the electrical terminal, of a first material; and a first adhesion improving layer coupled to the passivation layer and to the solid body, of a second material having predefined characteristics of adhesion to the first material, and configured to bond together the passivation layer and the solid body.

Abstract: A method includes generating a voltage proportional to absolute temperature, generating an uncorrected voltage complementary to absolute temperature, and generating a correction voltage. The method further includes selectively sampling the voltage proportional to absolute temperature, the uncorrected voltage complementary to absolute temperature, and the correction voltage, providing those sampled voltages to inputs of an integrator, and then quantizing outputs of the integrator to produce a bitstream. The method continues with causing the integrator to integrate the voltage proportional to absolute temperature or causing the integrator to add the correction voltage to the uncorrected voltage complementary to absolute temperature to produce a corrected voltage complementary to absolute temperature and then integrate the corrected voltage complementary to absolute temperature, depending upon a most recent bit of the bitstream.

Abstract: A body of semiconductor material has a surface and accommodates an active area, conductive regions, a first deep insulation structure extending in the active area from the surface of the body in a first trench, and a second deep insulation structure extending in the active area from the surface of the body in a second trench and surrounding the conductive regions. The first deep insulation structure has insulation walls surrounding a conductive filling portion. The second deep insulation structure has a solid insulating region filling the second trench. The first deep insulation region has a first width and a first depth and the second deep insulation structure has a second width and a second depth. The second width is smaller than the first width and the second depth is smaller than the first depth.

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

Abstract: An AFSM core includes a destination state-cell generating a destination state-signal, and a source state-cell generating a source state-signal and causing transition of the source state-signal in response to an acknowledgement indicating transition of the destination state-signal. The acknowledgment is communicated through a delay. A state-overlap occurs between transition of the destination state-signal and transition of the source state-signal. An output-net includes a balanced logic-tree receiving inputs, including the destination state-signal, from the core, and an additional logic-tree cascaded with the balanced logic-tree to form an unbalanced logic-tree so an input to the additional logic-tree is provided by output from the balanced logic-tree and another input receives the source state-signal. Tree propagation time occurs between receipt of a transition in the destination state-signal by the balanced logic-tree and a resulting transition of the output from the balanced logic-tree.

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.

Abstract: In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register

Abstract: A control circuit for an electronic converter is generates a drive signal of the electronic converter by setting the drive signal to a first logic level in response to a switch-on signal, and to a second logic level in response to a switch-off signal. The control circuit comprises a valley detection circuit and a combinational logic circuit. The control circuit comprises a blanking circuit configured to generate the blanking signal by determining a blanking time, and asserting the blanking signal when the blanking time elapses since the start of the switch-on or the switch-off interval. The control circuit comprises a blanking time adaption circuit to adapt the blanking time as a function of a blanking time adaption signal based on the input voltage, and to increase the blanking time when the input voltage increases, and decrease the blanking time when the input voltage decreases.

Abstract: In an embodiment a method for measuring ambient light includes successively synchronizing optical signal acquisition phases with extinction phases of a disruptive light source, wherein the disruptive light source periodically provides illumination phases and the extinction phases, accumulating, in each acquisition phase, photo-generated charges by at least one photosensitive pixel comprising a pinned photodiode, wherein an area of the pinned photodiode is less than or equal to 1/10 of an area of the at least one photosensitive pixel, transferring, for each pixel, the accumulated photo-generated charges to a sensing node, converting, for each pixel, the transferred charges to a voltage at a voltage node and converting, for each pixel, the transferred charges to a digital number.

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

Abstract: A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.