Patents Assigned to STMicroelectronics
  • Publication number: 20240204017
    Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.
    Type: Application
    Filed: February 29, 2024
    Publication date: June 20, 2024
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Mickael FOUREL, Laurent-Luc CHAPELON
  • Publication number: 20240201773
    Abstract: Disclosed herein is a debug system including a host computer, a microcontroller, and a debug probe for interface therebetween for performing debug trace operations. The debug probe samples the current drawn by the microcontroller. The debug probe and host computer cooperate so as to acquire and accurately align trace data and the samples of the current drawn by the microcontroller. Techniques for performing this alignment are described herein and enable for accurate inferences to be drawn about the current drawn by the microcontroller during different program operations.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Sylvain CHAVAGNAT, Simon VALCIN
  • Publication number: 20240199408
    Abstract: A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 20, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Giorgio ALLEGATO, Lorenzo CORSO, Ilaria GELMI, Carlo VALZASINA
  • Publication number: 20240206039
    Abstract: A device is configured to operate in a first mode of operation during which the device is configured to receive a first supply voltage in a contactless manner. The device includes a light emitting element and a first circuit. The first circuit is configured to receive a second supply voltage generated from the first supply voltage. A first current is generated from the first supply voltage, independent from the second voltage, and applied to the light emitting element which is selectively turned on.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 20, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Albin PEVEC, Nejc SUHADOLNIK, Damjan BERCAN, Maksimiljan STIGLIC
  • Publication number: 20240199415
    Abstract: Disclosed herein is a process flow for forming a MEMS IMU including an accelerometer and a gyroscope each located in a separate sealed cavity maintained at a different pressure. Formation of the MEMS IMU includes the use of a first vHF release to etch a sacrificial layer underneath a structural layer containing the accelerometer and gyroscope and capping the device under formation to set both cavities at a first pressure. The floor of one of the cavities is formed to including a gas permeable layer. Formation further includes forming a chimney underneath the gas permeable layer and then performing a second vHF release to etch through the gas permeable layer and expose the cavity containing the gas permeable layer so that its pressure may be set to be different than that of the other cavity when the chimney is sealed.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Federico VERCESI, Andrea NOMELLINI, Paolo FERRARI
  • Publication number: 20240206133
    Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 20, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Francesco SALAMONE
  • Publication number: 20240201351
    Abstract: Method to provide a TOF estimate by a TOF device. The method comprises: generating an electric echo signal indicative of an ultrasonic echo signal returned by a target body by the ultrasonic source signal; determining an envelope signal indicative of an envelope of the electric echo signal; generating a first TOF estimate by processing the electric echo signal; determining an envelope signal portion of the envelope signal based on a non-PSOA hyperparameter; and generating a second TOF estimate by processing the envelope signal portion through PSOA, the second TOF estimate having a measurement accuracy value greater than that of the first TOF estimate. PSOA is optimized based on a PSOA hyperparameter set. The non-PSOA hyperparameter and the PSOA hyperparameter set are selected among a plurality of choices based on the first TOF estimate, so as to obtain the second TOF estimate which has greater accuracy than the first TOF estimate.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 20, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Davide RUGGIERO, Rosario SCHIANO LO MORIELLO
  • Publication number: 20240204114
    Abstract: A variable-capacitance diode is formed in a doped semiconductor substrate of a first conductivity type. The diode includes a first doped region of a second conductivity type in semiconductor substrate. A second doped region of the first conductivity type in a portion of the first doped region and a third doped region of second conductivity type in a further portion of the first doped region form a PN junction of the diode. First insulating trenches laterally delimit the each PN junction. Doped areas having a doping level heavier than the first doped region are provided within the first doped region under and in contact with a bottom of each first insulating trench. The diode is surrounded by a second insulating trench deeper than the first insulating trench.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 20, 2024
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Frederic MONSIEUR
  • Publication number: 20240204112
    Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a forst doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.
    Type: Application
    Filed: March 1, 2024
    Publication date: June 20, 2024
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Arnaud YVON, Lionel JAOUEN
  • Publication number: 20240200980
    Abstract: A microelectromechanical sensor device has a detection structure and an associated electronic circuitry, configured to receive, when the device is powered, an external power supply voltage and provided with a voltage regulator generating a regulated voltage and with at least one voltage domain powered by the regulated voltage. The electronic circuitry has a power supply management core, always powered by the external power supply voltage and which controls the voltage regulator to selectively interrupt the power supply of the voltage domain to implement: a first power-down condition wherein the voltage regulator is disabled; and a second power-down condition wherein the voltage regulator is enabled to power the aforementioned voltage domain through the regulated voltage, the first and the second power-down conditions being associated with absence of data acquisition and/or processing by the sensor device.
    Type: Application
    Filed: November 17, 2023
    Publication date: June 20, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Salvatore POLI, Carmela MARCHESE
  • Publication number: 20240204127
    Abstract: The present description concerns an avalanche photodiode comprising: a main PN junction adapted to being reverse-biased; and a plurality of semiconductor regions including at least: a first epitaxial semiconductor region of a first conductivity type; and a second semiconductor region of the second conductivity type, said second region being arranged to at least partially surround the first region, and comprising surfaces in contact with surfaces of said first region. The present description also concerns a method of manufacturing such a photodiode.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 20, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Antonin ZIMMER, Dominique GOLANSKI, Sebastien PLACE, Guillaume MARCHAND
  • Publication number: 20240203834
    Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.
    Type: Application
    Filed: March 4, 2024
    Publication date: June 20, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Fabio MARCHISI
  • Publication number: 20240201717
    Abstract: A microelectromechanical sensor device has a detection structure and an associated electronic circuitry; the electronic circuitry receives, when the microelectromechanical sensor device is powered, an external power supply voltage and is provided with a voltage regulator which generates a regulated voltage having a different value from the external power supply voltage and at least one voltage domain powered by the regulated voltage. The electronic circuitry has a power supply management core, always powered by the external power supply voltage and controlling the voltage regulator to interrupt power supply to the voltage domain and implement a first power-down condition of the microelectromechanical sensor device.
    Type: Application
    Filed: November 14, 2023
    Publication date: June 20, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Carmela MARCHESE, Salvatore POLI
  • Publication number: 20240202148
    Abstract: A computer system includes a central processing unit, a peripheral circuit configured to process data having a first format, a memory configured to store data intended for the peripheral circuit, the data having a second format distinct from the first format. The system includes a direct memory access controller configured, during a transmission of data from the memory towards the peripheral circuit, to recover data intended for the peripheral circuit and stored in the memory, to modify the format of the recovered data to obtain data having the first format, and to transmit the data according to the first format to the peripheral circuit. The central processing unit is configured to initialize a data transmission from the memory towards the peripheral circuit via the direct memory access controller.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 20, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Jean-Christophe BATLLO, Zied GRISSA, Delphine LE GOASCOZ, Gwendhal BORREMANS
  • Publication number: 20240205055
    Abstract: Provided is a receiver circuit that receives a differential signal including positive and negative spikes. A first comparator produces an intermediate set signal that includes a pulse at each positive spike of the differential signal, and a second comparator produces an intermediate reset signal that includes a pulse at each negative spike of the differential signal. A sensing circuit extracts a common-mode voltage signal from the differential signal and asserts a control signal when the amplitude of the common-mode voltage signal exceeds a threshold. A logic circuit asserts a masking signal for an interval in response to asserting the control signal and de-asserts the masking signal in response to the interval elapsing. The logic circuit produces a corrected set signal. The logic circuit produces a corrected reset signal. An output circuit generates an output signal from the corrected set signal and the corrected reset signal.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 20, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Valerio GENNARI SANTORI, Carlo CURINA, Valerio BENDOTTI, Nicola DE CAMPO
  • Publication number: 20240201873
    Abstract: A device executes an authentication process protected by an authentication counter that is incremented in case of an authentication failure. The incrementation of the counter is protected against unexpected device power-off or power-off attacks. A non-volatile memory is divided into pairs of cells. The protecting includes writing a fixed value D into an active pair of two consecutive cells. As long as successful authentications occur, the content of the first cell is overwritten by a random value. When a failed authentication occurs, the content of the second cell is overwritten by a random value and the next two consecutive cells are written with the fixed value D. Those cells form the active pair and the protection process is repeated. This mechanism facilitates preventing the lack of incrementation of the authentication counter in case of unexpected device power-off during the processing of a failed authentication.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 20, 2024
    Applicant: STMicroelectronics (Grand Ouest) SAS
    Inventors: Fabien ARRIVE, Yves MAGNAUD
  • Patent number: 12015515
    Abstract: A transmitter circuit receives a PWM input signal and a clock signal. A logic circuit generates a control signal as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than a half clock period of the clock signal. A tri-state transmitter receives the PWM input signal and the control signal, and produces first and a second output signals at first and second transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage and a reference voltage. An output control circuit is sensitive to the control signal and is coupled to the first and second transmitter output nodes.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: June 18, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Valerio Bendotti, Nicola De Campo, Carlo Curina
  • Patent number: 12011269
    Abstract: In an embodiment, a method of processing an electrophysiological signal includes collecting the electrophysiological signal that is indicative of a level of attention of a human; filtering the electrophysiological signal via joint low-pass and high-pass filtering using a set of filtering parameters including low-pass filters parameters and high-pass filters parameters having a set of low-pass cut-off frequencies and a set of high-pass cut-off frequencies respectively. The method further includes applying artificial neural network processing to the filtered electrophysiological signal to extract therefrom a set of features of the electrophysiological signal. The method further includes applying classifier processing to the set of features extracted from the filtered electrophysiological signal and producing a classification signal indicative of the level of attention of the human. The method further includes generating a trigger signal to trigger a user circuit based on the classification signal.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: June 18, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Francesco Rundo, Sabrina Conoci
  • Patent number: 12015243
    Abstract: A laser diode driver circuit includes a first pair of contacts and connectors coupled to an anode of the laser diode. An inductance of each of the first pair of contacts and connectors is the same. A second pair of contacts and connectors are coupled to a cathode of the laser diode. An inductance of each of the second pair of contacts and connectors is the same. The laser diode driver circuit also includes current driving circuitry.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: June 18, 2024
    Assignees: STMICROELECTRONICS (RESEARCH & DEVELOPMENT ) LIMITED, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Denise Tingxi Lee, Neale Dutton, Nicolas Moeneclaey, Jerome Andriot-Ballet
  • Patent number: 12015427
    Abstract: An input stage circuit for a sigma-delta analog-to-digital converter circuit receives a digital-to-analog converter generated feedback signal and an analog current input signal to generate a difference signal applied to an integrator circuit. A single bit quantization circuit quantizes an output of the integrator circuit to generate a bit signal that is applied to an input of the digital-to-analog converter. The input stage circuit includes a switched input capacitor controlled by first and second, non-overlapping, clock signals.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: June 18, 2024
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Ilina Todorova, Jeffrey M. Raynor