Patents Assigned to STMicroelectronics
  • Patent number: 8766435
    Abstract: An integrated circuit package is provided with a thin-film battery electrically connected to and encapsulated with an integrated circuit die. The battery can be fabricated on a dedicated substrate, on the die pad, or on the integrated circuit die itself.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: Michael J. Hundt, Haibin Du, Krishnan Kelappan, Frank Sigmund
  • Patent number: 8764874
    Abstract: A request routing circuit includes m inputs for receiving m input request signals and n outputs for outputting a set of n output request signals. A routing subsystem within the request routing circuit is provided between the m inputs and the n outputs and comprises k inputs and n outputs, where m is greater than k, and where the routing subsystem is configured to operate over a plurality (m/k, rounded up to the next integer) of cycles to provide the set of n output request signals based on the m inputs to the n outputs.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Davide Sarta, David Smith
  • Patent number: 8767053
    Abstract: Methods and systems are described for enabling the viewing of positionally and orientationally modified stereoscopic video material using one or more participants with near-to-eye displays with video content appearance altered to accommodate changes in orientation and position of the display.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Greg Neal
  • Patent number: 8767955
    Abstract: A method for protecting a calculation, by an electronic circuit, of a modular exponentiation of a digital quantity, wherein: a first variable is initialized with a random quantity; at least one second variable is initialized with a value which is a function of the digital quantity; at least for a bit at 1 of an exponent of the modular exponentiation, the first variable is updated by: a) the quotient of its content and a power of the random quantity; and b) the product of its content by that of the second variable; and once all the exponent bits have been processed, the content of the first variable is divided by the random quantity to provide the result of the modular exponentiation.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Patent number: 8766164
    Abstract: An embodiment of a Geiger-mode avalanche photodiode includes a body of semiconductor material having a first conductivity type, a first surface and a second surface; a trench extending through the body from the first surface and surrounding an active region; a lateral-isolation region within the trench, formed by a conductive region and an insulating region of dielectric material, the insulating region surrounding the conductive region; an anode region having a second conductivity type, extending within the active region and facing the first surface. The active region forms a cathode region extending between the anode region and the second surface, and defines a quenching resistor. The photodiode has a contact region of conductive material, overlying the first surface and in contact with the conductive region for connection thereof to a circuit biasing the conductive region, thereby a depletion region is formed in the active region around the insulating region.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato Sanfilippo, Massimo Cataldo Mazillo
  • Patent number: 8764997
    Abstract: A method of metal deposition may include chemically modifying a surface of a substrate to make the surface hydrophobic. The method may further include depositing a layer of metal over the hydrophobic surface and masking at least a portion of the deposited metal layer to define a conductive metal structure. The method may also include using an etching agent to etch unmasked portions of the deposited metal layer.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Fabrizio Porro, Luigi Giuseppe Occhipinti
  • Patent number: 8765575
    Abstract: A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO2 layer and penetrating into a silicon support, this method including the steps of forming on the silicon layer a second SiO2 layer and a first silicon nitride layer, forming the trench, and performing a first oxidizing processing to form a third SiO2 layer; performing a second oxidizing processing to form, on the exposed surfaces of the first silicon nitride layer a fourth SiO2 layer; depositing a second silicon nitride layer and filling the trench with SiO2; and removing the upper portion of the structure until the upper surface of the silicon layer is exposed.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Laurent Favennec
  • Patent number: 8767428
    Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics International N. V.
    Inventor: Vivek Asthana
  • Publication number: 20140176587
    Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.
    Type: Application
    Filed: March 3, 2014
    Publication date: June 26, 2014
    Applicant: STMicroelectronics, Inc
    Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
  • Publication number: 20140175649
    Abstract: An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: STMicroelectronics Pte. Ltd
    Inventors: Yonggang Jin, Yun Liu, Yaohuang Huang
  • Publication number: 20140175554
    Abstract: Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate. Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate. The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: STMICROELECTRONICS , INC.
    Inventors: Nicolas Loubet, Prasanna Khare
  • Publication number: 20140175610
    Abstract: A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Publication number: 20140175541
    Abstract: A method for integrating a set of electronic devices on a wafer (100; 200a; 200b) of semiconductor material having a main surface includes forming a plurality of trenches extending into the wafer from the main surface. At least one layer of electrically insulating material is formed within each trench. At least one layer of electrically conductive material is formed within each trench superimposed on the at least one layer of insulating material. The formation of the plurality of trenches includes forming the trenches partitioned into sub-sets of trenches. The trenches of a first sub-set are oriented along a first common direction that is different from the orientation of the trenches of a second sub-set.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 26, 2014
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Angelo Matri', Francesco Lizio
  • Patent number: 8759174
    Abstract: A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the device, implanting doping ions of a first type into the first region, implanting doping ions of a second type into the second region, and etching the first and second regions for a determined duration such that the first silicon oxide layer is removed and at least a part of the second silicon oxide layer remains.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: June 24, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A., NXP B.V.
    Inventors: Markus Müller, Alexandre Mondot, Pascal Besson
  • Patent number: 8759898
    Abstract: A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: June 24, 2014
    Assignee: STMicroelectronics S.A.
    Inventor: Pascal Fornara
  • Patent number: 8760461
    Abstract: Methods, chips, systems, computer program products and data structures are described for conducting modification of color video signals from a first color format associated with an originating format to a second format compatible with a display media of a display device.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: June 24, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: Osamu Kobayashi, Zisheng Le
  • Patent number: 8760132
    Abstract: Disclosed is an output stage, and associated apparatus, for a voltage regulator that includes a clamp circuit that is operable to ensure that the output voltage recovers quickly, i.e. that the perturbation of this voltage is limited and remains within a given specification, when entering a standby mode and which is controlled in a supply independent manner.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: June 24, 2014
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Dayananda Kumar Rasaratnam
  • Patent number: 8759965
    Abstract: A protective modular package assembly with one or more subassemblies, each having a base element, a sidewall element coupled to the base element, and a semiconductor device disposed within and coupled to the sidewall element and the base element; a protective modular package cover having fastening sections located at opposing ends of the cover, torque elements disposed on the opposing ends and configured to fasten the cover to a core, and subassembly receiving sections disposed between the fastening sections with each subassembly receiving section operable to receive a subassembly and having a cross member along the underside of the cover; and an adhesive layer configured to affix subassemblies to respective subassembly receiving sections. The torque elements are configured to transfer a downward clamping force generated at the fastening elements to a top surface of the subassemblies via the cross member of each of the one or more subassembly receiving sections.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: June 24, 2014
    Assignees: STMicroelectronics, Inc., RJR Polymers, Inc.
    Inventors: Craig J. Rotay, John Ni, David Lam, David Lee DeWire, John W. Roman, Richard J. Ross
  • Patent number: 8760952
    Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: June 24, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: David V. Carlson
  • Patent number: 8762590
    Abstract: A communication system for an HDMI communication interface CEC channel includes a communication module for receiving messages via the CEC channel, a processing unit for processing the received messages and an oscillator for driving the communication module. When the interface is in an active mode, the system is operative to activate the timer upon detection of the start of transmission of a first message, detect the initial bit of the first message, reconstruct and process the first message, and switch the interface from the active mode to standby by deactivating the oscillator. When the interface is in standby, the system is operative to switch the interface to the active condition by activating the oscillator and the timer when the start of a transmission of a second message is detected, detect the initial bit of a transmission of the second message, and reconstruct and process the second message.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: June 24, 2014
    Assignee: STMicroelectronics s.r.l.
    Inventors: Ugo Mari, Francesco Bombaci, Pietro Cusmano, Sonia Sfasciotti