Abstract: A structure for protecting an integrated circuit connected to first and second rails of a differential link against overvoltages, including: a first bidirectional conducting device, between the first rail and a common node; a second bidirectional conducting device, between the second rail and the common node; and a capacitor between the common node and a low reference potential rail.

Abstract: A thermoelectric generator including a sheet of a deformable material containing closed cavities, each of which contains a drop of a vaporizable liquid, and a mechanism for transforming into electricity the power resulting from the deformation of the sheet linked to the evaporation/condensation of the liquid.

Abstract: A memory repair mechanism for the memories clustered across the multiple power domains and can be switched on and off independent of each other, thereby enabling low power operation. Enhancements in the shared Fuse Wrapper Architecture enable sharing of a plurality of parallel links connecting the memory blocks of each power domains to the Shared Fuse Wrapper architecture.

Abstract: An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.

Abstract: An embodiment of communication cell for enabling data communication between an integrated circuit and an electronic unit distinct from the integrated circuit, comprising a contact pad unit, configured for capacitively coupling, in a first operating condition of said communication cell, to the electronic unit for receiving an input signal from said electronic unit, and for ohmically coupling, in a second operating condition of said communication cell, to the electronic unit for receiving the input signal; a receiver device, including signal-amplifying means, coupled between said contact pad unit and said integrated circuit, configured for receiving the input signal and generating an intermediate signal correlated to the input signal; signal-selection means receiving the intermediate signal, the input signal, and providing an output signal which is the intermediate signal during the first operating condition, and the input signal during the second operating condition; and an input stage, connectable between the

Abstract: An electronic circuit in a package, including two functions, the package orientation activating a single one of the two functions.

Abstract: A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit.

Abstract: A directional dual distributed coupler including: a first conductive line between first and second ports, intended to convey a signal to be transmitted in a first frequency band; a second conductive line coupled to the first one; a third conductive line between third and fourth ports, intended to convey a signal to be transmitted in a greater frequency band than the first one; a fourth conductive line coupled to the third one; and at least one diplexer connecting, on the side of the second and fourth ports, the respective ends of the second and fourth lines to a fifth port.

Abstract: A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.

Abstract: A control device for a switching circuit of a resonant converter having a direct current at the output, the switching circuit having at least one half bridge of at least first and second transistors connected between an input voltage and a reference voltage. The half bridge is adapted to generate a periodic square wave voltage to drive the resonant circuit of the resonant converter; The control device has a circuit to proportionally generate a first voltage to a switching period, and a circuit adapted to limit the voltage at the ends of a capacitor between a reference voltage and the first voltage, and a further circuit structured to control the switching off of a first or second transistor at the time instant in which the voltage across the capacitor has reached the first voltage.

Abstract: A class AB operational amplifier includes an input stage, an output stage and a level shifter stage to control the quiescent current of the output stage and to transfer the signal from the input stage to the output stage, and a control circuit of the level shifter stage. The control circuit includes a transistor differential pair having a differential input terminals and the differential voltage at the differential terminals of the differential pair controls the level shifter stage.

Abstract: A distributed-line directional coupler including: a first conductive line between first and second ports intended to convey a signal to be transmitted; and a second conductive line, coupled to the first one, between third and fourth ports, the second line being interrupted approximately at its middle, the two intermediary ends being connected to attenuators.

Abstract: A video processor includes a spatio-temporal noise reduction controller to determine current and previous image edge slopes and adaptively control a spatio-temporal noise reduction processor to blend current and previous images dependent on the current and previous image edge slope values.

Abstract: A wireless device belongs to a wireless communication system and exchanges information within at least one band of frequencies. A method includes detecting a presence of at least one victim device operating within the at least one band of frequencies. The first wireless device is provided with an antenna array, and the detecting step includes analyzing an environment of the wireless device through the antenna array, and if the at least one victim device is detected, reducing interference by controlling the antenna array to steer the antenna beam toward an area located outside a vicinity of the potential victim device to exchanging information within the at least one band of frequencies with at least a second wireless device located in the area.

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract: A driver for an electric load includes a power device having a control terminal and an output terminal for an output current, and a control module. The control module is configured to drive the power device in an auto-recovery mode by switching between activation and deactivation in the occurrence of an overcurrent condition, wherein the output current reaches a threshold current. The control module is also configured to evaluate a first time interval between a time wherein the overcurrent condition occurs, and a first time, and generate a limit signal when the time interval is equal to a time threshold. The power device is driven in a switching-off condition at least as a function of the limit signal.

Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.

Abstract: A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.

Abstract: An oscillator module includes a first MOS transistor and a capacitor. The capacitor is coupled between a gate and source of the first MOS transistor. The drain of the first MOS transistor receives a first bias current and generates an oscillating output signal. A switching circuit operates in response to the oscillating output signal to selective charge and discharge the capacitor. A current sourcing circuit is configured to generate the bias current. The current sourcing circuit includes a second MOS transistor which has an identical layout to the first MOS transistor and receives a second bias current. A resistor is coupled between a gate and source of the second MOS transistor. The current sourcing circuit further includes a current mirror having an input configured to receive a reference current passing through the resistor and generate the first and second bias currents.

Abstract: Disclosed embodiments are directed to methods, systems, and circuits of generating compact descriptors for transmission over a communications network. A method according to one embodiment includes receiving an uncompressed descriptor, performing zero-thresholding on the uncompressed descriptor to generate a zero-threshold-delimited descriptor, quantizing the zero-threshold-delimited descriptor to generate a quantized descriptor, and coding the quantized descriptor to generate a compact descriptor for transmission over a communications network. The uncompressed and compact descriptors may be 3D descriptors, such as where the uncompressed descriptor is a SHOT descriptor. The operation of coding can be ZeroFlag coding, ExpGolomb coding, or Arithmetic coding, for example.