Abstract: An encapsulated micro-electro-mechanical device, wherein a MEMS chip is encapsulated by a package formed by a first, a second, and a third substrates that are bonded together. The first substrate has a main surface bearing the MEMS chip, the second substrate is bonded to the first substrate and defines a chamber surrounding the MEMS chip, and the third substrate is bonded to the second substrate and upwardly closes the chamber. A grid or mesh structure of electrically conductive material is formed in or on the third substrate and overlies the MEMS chip; the second substrate has a conductive connection structure coating the walls of the chamber, and the first substrate incorporates an electrically conductive region, which forms, together with the conductive layer and the grid or mesh structure, a Faraday cage.

Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a first region adjacent to a second region itself adjacent to at least one third region, the first, second, and third regions each extending from the upper electrode to the lower electrode, the crystallization temperature of the second region ranging between that of the first region and that of the third region, and the melting temperatures of the first, second, and third regions being substantially identical.

Abstract: For enhanced interoperability of safety and non-safety communications, a synchronous interval is divided into a safety channel interval and an open interval instead of a CCH (control channel) interval and SCH (service channel) interval. For a single-radio device, a control interval, in place of an open interval should be scheduled at least once every maximum service scheduling period. Such a control interval is dedicated for CCH (and SCH) operation. For a multi-radio device, a control interval is scheduled at least once every maximum control interval on one of the radios support non-safety services (e.g. tolling).

Abstract: Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins can be grown epitaxially from the silicon surface, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed, while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate.

Abstract: A method for integrating a bipolar injunction transistor in a semiconductor chip includes the steps of forming an intrinsic base region of a second type of conductivity extending in the collector region from a main surface through an intrinsic base window of the sacrificial insulating layer, forming an emitter region of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window of the sacrificial insulating layer, removing the sacrificial insulating layer, forming an intermediate insulating layer on the main surface, and forming an extrinsic base region of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window of the intermediate insulating layer.

Abstract: Two suspended masses are configured so as to be flowed by respective currents flowing in the magnetometer plane in mutually transversal directions and are capacitively coupled to lower electrodes. Mobile sensing electrodes are carried by the first suspended mass and are capacitively coupled to respective fixed sensing electrodes. The first suspended mass is configured so as to be mobile in a direction transversal to the plane in presence of a magnetic field having a component in a first horizontal direction. The second suspended mass is configured so as to be mobile in a direction transversal to the plane in presence of a magnetic field having a component in a second horizontal direction, and the first suspended mass is configured so as to be mobile in a direction parallel to the plane and transversal to the current flowing in the first suspended mass in presence of a magnetic field having a component in a vertical direction.

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract: A method of adjustment during manufacture of a capacitance of a capacitor supported by a substrate, the method including the steps of: a) forming a first electrode parallel to the surface of the substrate and covering it with a dielectric layer; b) forming, on a first portion of the dielectric layer, a second electrode; c) measuring the electrical signal between the first electrode and the second electrode, and deducing therefrom the capacitance to be added to obtain the desired capacitance; d) thinning down a second portion of the dielectric layer, which is not covered by the second electrode, so that the thickness of this second portion is adapted to the forming of the deduced capacitance; and e) forming a third electrode on the thinned-down portion and connecting it to the second electrode.

Abstract: A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.

Abstract: This invention relates to a method of receiving a first potentially unreliable clock signal having a first frequency; receiving a second reliable clock signal having a second frequency; wherein the first frequency and the second frequency have an expected relationship; determining whether the first potentially unreliable clock signal has changed with respect to the second reliable clock signal by: determining an actual relationship between the first potentially unreliable frequency and the second reliable frequency; and generating an alarm signal if the actual relationship is different to the expected relationship.

Abstract: A method for automatic design of an electronic circuit, includes: generating (100) a layout (L) of the aforesaid electronic circuit; generating (200) abstract data (A) at the substrate level associated to the layout (L) of the aforesaid electronic circuit; generating (300) a grid (TG) of subdivision into meshes and nodes with respect to a view pertaining to the aforesaid abstract (A) and applying it to the aforesaid substrate (SBS); and extracting (400), on the basis of the aforesaid subdivision grid (TG), a full electrical netlist (NC) pertaining to the substrate (SBS). The method further includes performing an evaluation (500, 600) of the interactions between devices (DV) of the electronic circuit at the substrate level according to the aforesaid full electrical netlist (NC) pertaining to the substrate (SBS).

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches,=; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.

Abstract: An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.

Abstract: An arc fault detection circuit includes a current sensing circuit coupled to a line conductor carrying a current. The current sensing circuit operates to sense current and output data indicative of the sensed current. A processing circuit implements a frequency transform algorithm to transform the output data to frequency data in a low frequency range and with a high spectral resolution where a minimum short time observation window is concerned. The processing circuit identifies an arc fault condition on the line conductor by identifying differences in said frequency data between at least two subsequent observation windows and identifying characteristics which exceed thresholds.

Abstract: An electronic power component including a normally on high-voltage transistor and a normally off low-voltage transistor. The normally on transistor and the normally off transistor are coupled in cascode configuration and are housed in a single package. The normally off transistor is of the bottom-source type.

Abstract: A SIM card adapter assembly is to adapt a SIM card to a SIM slot. The adapter assembly includes a SIM card plastic support including a first portion of a predetermined thickness. The SIM card is removably attached and a second portion has an increased thickness wherein at least one adapter is removably attached.

Abstract: A device includes an image sensor and a circuit for controlling the sensor. The control circuit is configured control the device in a first operating mode and second operating mode. In the first operating mode images acquired by the sensor are output. In the second operating mode, no images are provided, but a selected subassembly of pixels of the image sensor are read and image data therefrom is processed to provide an ambient luminosity value.

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract: A chain of switches is connected between a first power supply line coupled to a first voltage and a second power supply line coupled to the sector. These switches are controllable by a control signal. The control signal is propagated from a first end of the first chain towards a second end of the first chain without control of the switches during this first propagation. The control signal is then propagated in the reverse direction from the second end towards the first end with a control of the switches during this second propagation starting from a group of at least one switch situated at the second end. There is a detection of the arrival of the control signal at the first end of the chain at the end of its propagation in the reverse direction.