Patents Assigned to STMicroelectronics
  • Publication number: 20140140354
    Abstract: Transmission of data frames over a channel in a communications network takes place on a slotted time base. A method comprises an evaluation, by at at least one node of the network having a frame available for transmission, of whether the channel is available for transmission. If the the channel is available for transmission, the available frame is transmitted over the channel in a subsequent slot of the slotted time base. If the channel is not available for transmission, owing to a frame (having a certain temporal length) being transmitted over the channel at a certain time, the slotted time base of the at least one node is resynchronized as a function of the frame being transmitted. The resynchronization includes identifying, as a function of the certain temporal length, an interval of delay to evaluate again in at a furture time whether the channel is available for transmission.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 22, 2014
    Applicant: STMicroelectronics Srl
    Inventors: Vincenzo Mormina, Elio Rosario Blanca
  • Publication number: 20140138814
    Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.
    Type: Application
    Filed: October 9, 2013
    Publication date: May 22, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Abderrezak Marzaki, Yoann Goasduff, Virginie Bidal, Pascal Fornara
  • Publication number: 20140139029
    Abstract: A dual input single output (DISO) regulator, includes a comparator configured to receive a first and second power supply signal and to provide a first compared signal; a first switch configured to couple the first power supply source to an intermediate node, and a second switch configured to couple the second power supply source to the intermediate node; a control logic circuit, coupled to the first comparator, to the first switch, and to the second switch, and configured to receive the compared signal to control the first and the second switch in a first and second operating condition based on the compared signal. The intermediate node being biased by an intermediate power supply signal correlated to the first or second power supply signal. The DISO regulator includes a low-dropout regulator, configured to provide a regulated power supply signal based on the intermediate power supply signal.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Gasparini, Andrea Donadel, Stefano Ramorini
  • Publication number: 20140138834
    Abstract: In a general aspect, an integrated circuit package includes a first electrode and a second electrode on a support substrate. The first electrode and the second electrode are configured to be electrically coupled to a voltage differential. A dendritic migration of a migratory species can develop under the voltage differential and a non-hermetic environment. The dendritic migration is interrupted by a floating electrical barrier mounted onto the support substrate between the first electrode and the second electrode. The electrical barrier includes a dam for preventing the metal migration. The dam has a height approximately equal to or greater than the largest dimension of a single atom of the migratory species. The first electrode and the second electrode can be mounted on the same side of the support substrate, or on two opposite sides of the support substrate.
    Type: Application
    Filed: September 16, 2013
    Publication date: May 22, 2014
    Applicant: STMICROELECTRONICS, INC.
    Inventors: John C. Pritiskutch, Richard R. Hildenbrandt
  • Publication number: 20140140423
    Abstract: In an embodiment, a transmitter includes a transmission path configurable to generate first pilot clusters in response to a matrix, each first pilot cluster including a respective first pilot subsymbol in a first cluster position and a respective second pilot subsymbol in a second cluster position such that a vector formed by the first pilot subsymbols is orthogonal to a vector formed by the second pilot subsymbols, the matrix having a dimension related to a number of cluster positions in each of the first pilot clusters. For example, where such a transmitter transmits simultaneous orthogonal-frequency-division-multiplexed (OFDM) signals (e.g., MIMO-OFDM signals) over respective channels that may impart inter-carrier interference (ICI) to the signals due to Doppler spread, the pattern of the pilot symbols that compose the pilot clusters may allow a receiver of these signals to estimate the responses of these channels more accurately than conventional receivers.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 22, 2014
    Applicants: STMICROELECTRONICS, INC., STMICROELECTRONICS ASIA PACIFIC PTE LTD.
    Inventors: Karthik MURALIDHAR, George A. VLANTIS
  • Publication number: 20140138832
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Chengyu Niu, Andrew Simon, Keith Kwong Hon Wong, Yun-Yu Wang
  • Publication number: 20140138739
    Abstract: An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Angelo MAGRI', Antonino Sebastiano ALESSANDRIA, Stefania FORTUNA, Leonardo FRAGAPANE
  • Publication number: 20140141603
    Abstract: An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Ferruccio FRISINA, Mario Giuseppe SAGGIO, Angelo MAGRI'
  • Patent number: 8729974
    Abstract: A crystal oscillator circuit is configured to output an oscillation signal. A bias circuit responds to control signal to generate a bias current for application to the crystal oscillator circuit. A current generator generates a sense current from the control signal. The sense current is compared to a reference current by a comparator circuit. The comparator circuit generates a ready signal in response to the comparison. The ready signal is indicative of whether the oscillation signal output from the crystal oscillator circuit is ready for use by other circuitry. The reference current may be generated by a circuit which replicates the bias circuit.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giulio Zoppi, Raffaele Iardino
  • Patent number: 8727504
    Abstract: Disclosed herein is a microfluidic jetting device having a piezoelectric member positioned above a displaceable membrane. A voltage is applied across the piezoelectric member causing deformation of the piezoelectric member. The deformation of the piezoelectric member results in a displacement of the membrane, which is formed above a cavity. Displacement of the membrane creates pressure to jet or eject liquid from the cavity and suction liquid into the cavity through ports or apertures formed in the in membrane.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Michele Palmieri
  • Patent number: 8730756
    Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 20, 2014
    Assignees: STMicroelectronics International N.V., STMicroelectronics, SA
    Inventors: Nishu Kohli, Robin M. Wilson
  • Patent number: 8729701
    Abstract: The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas Jourdan, Joaquin Torres
  • Patent number: 8732729
    Abstract: The present invention provides a technical solution for a unified driver used in a handheld device. An embodiment of the technical solution may comprise a unified driving method used in a handheld device, which method may comprise: determining driver types of currently installed hardware; setting a current dispatch table on the basis of the driver type and a unified dispatch table suitable for multiple hardware and driving corresponding hardware or software by calling the current dispatch table.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics R&D (Shanghai) Co., Ltd.
    Inventors: Christophe Quarre, Maoping Weng, Zhe Wu
  • Patent number: 8732372
    Abstract: Methods and systems are described for displaying enabling the transmission, formatting, and display of multimedia data after a hot plug event during a start-up dead period. In particular, approaches for transmission, formatting, and display of multimedia data in the absence or non-operation of a hot plug detect system or signal, so that multimedia information can be displayed in a proper format even during the dead period when no hot plug detect signal is received.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Alan Osamu Kobayashi
  • Patent number: 8731041
    Abstract: A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Canada) Inc.
    Inventors: Anton Pelteshki, John Hogeboom
  • Patent number: 8730953
    Abstract: A method for communicating video data on a wireless channel in a packet-switched network includes the steps of operating at a wireless terminal a compression in packets on the video data during a video coding operation, detecting wireless channel conditions and adapting control parameters of the video coding operation to the detected wireless channel conditions. The compression operation is a robust header compression operation and the step of adapting control parameters of said video coding operation is performed depending on information about the wireless channel conditions detected on a feedback channel made available in a decompression step associated with the compression operation.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics s.r.l.
    Inventors: Diego Melpignano, Stefano Olivieri
  • Patent number: 8731214
    Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Anupam Jain, Rakhel Kumar Parida
  • Patent number: 8730707
    Abstract: The programming of a read-only memory formed of MOS transistors is set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors. The programming of the read-only memory cannot be determined by visible inspection of the memory.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 8730072
    Abstract: The present disclosure includes calibration circuitry for adjusting the bandwidth of at least one sub-converter of an interleaved analog to digital converter (ADC), the at least one sub-converter having an input switch coupled to an input line of the ADC, the calibration circuitry having a control circuit adapted to adjust a bulk voltage of a transistor forming the input switch.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Roger Petigny, Hugo Gicquel, Fabien Reaute
  • Patent number: 8729702
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 20, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Chengyu Niu, Andrew Simon, Keith Kwong Hon Wong, Yun-Yu Wang