Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

Abstract: A voltage regulator circuit includes a differential amplifier stage. The gate terminal of a first n-channel MOSFET is coupled to an output of the differential amplifier stage. A resistor is coupled between the drain terminal and gate terminal of the first n-channel MOSFET. The drain terminal of the first n-channel MOSFET drives the gate of a second n-channel MOSFET whose drain terminal is at the input of a current mirror circuit. An output of the current mirror circuit forms the regulated voltage output. A feedback circuit is coupled between the regulated voltage output and one input of the voltage regulator circuit. Another input of the voltage regulator circuit is configured to receive a reference voltage.

Abstract: A dryer having an improved automatic dryness detection circuit is provided. Wet clothing in the dryer bin contacts a sensor and causes a pulse to be sent to a microcontroller if the resistance of the clothes is low enough. The microcontroller disregards pulses which are shorter than a threshold time and counts pulses which are longer than a threshold time. The microcontroller issues a termination signal if the rate of pulses is lower than a threshold rate.

Abstract: A 3-D structure formed in a recess of a substrate delimited by walls, including a large number of rectangle parallelepipedic blades extending from the bottom of the recess to the substrate surface while being oriented perpendicularly to one another and formed in a pattern covering the whole surface of the recess, some blades being non-secant to one of the walls, each non-secant blade being connected to one of the walls by at least another perpendicular blade.

Abstract: A method for controlling the power supply of an integrated circuit, the power supply comprising a power supply unit powered by a main voltage and possessing several transistor groups, comprising turning on in succession at least two transistor groups in order to deliver, as an output from each group, to at least one part of the integrated circuit, an elementary supply voltage derived from the main voltage, characterized in that the method comprises at least one elementary power phase for supplying power to said at least one part of the integrated circuit, wherein the phase comprises defining voltage thresholds respectively associated with the transistor groups, turning on a first transistor group, the first group delivering a first elementary supply voltage and turning on at least one second group when the first elementary supply voltage is higher than or equal to the voltage threshold associated with the second group.

Abstract: A transmission channel configured to transmit high-voltage pulses and to receive echos of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.

Abstract: An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level.

Abstract: A switched capacitor amplifier having an amplification unit adapted to amplify a differential signal; a first switched capacitor block including a first plurality of capacitors operable to sample a first differential input signal during a first sampling phase and to drive the amplification unit during a first drive phase; and a second switched capacitor block including a second plurality of capacitors operable to sample a second differential input signal during a second sampling phase and to drive the amplification unit during a second drive phase.

Abstract: A method for manufacturing a TiN/Ta2O5/TiN capacitor, including the steps of forming a Ta2O5 layer on a TiN support by a plasma-enhanced atomic layer deposition method, or PEALD; and submitting the obtained structure to an N2O plasma for a duration sufficient to oxidize the Ta2O5 layer without oxidizing the TiN support.

Abstract: A method and a system for transferring a digital signal through a transformer, in which the current in a primary winding of the transformer is a frequency-modulated signal exhibiting sinusoidal trains of different durations according to the rising or falling edge of the digital signal to be transferred.

Abstract: A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.

Abstract: A multichannel splitter formed from 1 to 2 splitters, wherein: an input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter; the 1 to 2 splitters are electrically series-connected; and first respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.

Abstract: A battery includes a battery module that includes a plurality of submodules electrically connected in series. Each submodule comprises first and second submodule terminals and a cell. At least one submodule in each battery module is a switchable submodule comprising a submodule switching circuit. The submodule switching circuit is switchable between a first state and a second state. The submodule switching circuit electrically connects the cell of the switchable submodule between the first and second submodule terminals when the submodule switching circuit is in the first state. The submodule switching circuit provides an electrical bypass connection between the first and second submodule terminals and the cell of the switchable submodule is electrically disconnected from at least one of the first and second submodule terminals when the switching circuit is in the second state. The battery further comprises a control unit for operating the switching circuit of each module.

Abstract: A method comprises depositing an optical filter layer on a glass wafer, then cutting the wafer into dice. The dice are positioned on a carrier and encapsulated in a molding compound to form a reconstituted wafer, and the wafer is back-ground and polished. Lens faces are positioned on opposing surfaces of the glass dice and spacers are positioned on one side of the wafer. The wafer is then cut into lens modules, each having two side-by-side lenses with an opaque molding compound barrier between. The individual modules are attached to devices that require dual lenses, such as, e.g., proximity sensors that use a light source and a light receiver or detector.

Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.

Abstract: Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer.

Abstract: An apparatus includes an output configured to output data to a communication path of an interconnect for routing to a target and a rate controller configured to control a rate of the output data. The rate controller is configured to control the rate in response to feedback information from the target.

Abstract: A device and method for writing/reading a piece of data in/from a memory register shared by a plurality of peripherals, each peripheral having a peripheral clock signal, when two or more of the plurality of peripherals need to write/read such piece of data at the same time, the digital device including a central unit having the memory register and a bank of SL modules in signal communication with the central unit, the bank of SL modules being designed to write/read the piece of data.

Abstract: An electronic system for driving a lamp of a blinker of a vehicle may include a switch having a first input terminal configured to receive a battery voltage, a second input control terminal configured to receive a control signal for operating the switch, and an output terminal. The system may also include a change-over switch configured to connect, alternatively, the output terminal of the switch to the lamp and to a high impedance reference. The system may also include an electronic device connected to the switch and configured to detect a voltage drop between the first input terminal and the output terminal, and, based upon the voltage drop, generate the control signal to have a value to maintain the switch open for a time interval, and generate the control signal to have a second value to maintain the switch closed for another time interval.

Abstract: An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively.