Abstract: A method and apparatus are disclosed for identifying and removing banding artifacts (i.e., false contours) resulting from insufficient bit depth caused by digital image quantization, conversion, and/or compression. This method includes: explicitly identifying texture block and flat block; de-termination of filter window sizes with the consideration of handling transitions between texture block and flat block; de-banding filtering with edge protection; and noise shaping according to de-banding filter result.
Type:
Grant
Filed:
November 23, 2011
Date of Patent:
May 20, 2014
Assignee:
STMicroelectronics Asia Pacific Pte Ltd.
Abstract: A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer.
Type:
Grant
Filed:
June 15, 2012
Date of Patent:
May 20, 2014
Assignees:
STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
Abstract: A method detects metallic atoms in a fluid. The method includes: placing, in a zone sheltered from light, a photodiode comprising a photosensitive surface in contact with a fluid to analyze; heating the photosensitive surface of the photodiode to a temperature sufficient to allow metallic atoms deposited on the photosensitive surface to migrate through this surface; acquiring a signal relative to the lighting of the photodiode; and determining, from the acquired signal, a measurement representative of a contamination status by metallic atoms of the photodiode.
Abstract: An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.
Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed<=V2 and b) Vhigh?Vmed<=V1. If the drive circuit is a high side driver, the intermediate voltage node receives an intermediate voltage Vmed set below the high supply voltage and that mees the following conditions: a) Vmed<=V1 and b) Vhigh?Vmed<=V2. The circuit may be configured as a push pull driver by coupling a high side driver and low side driver in series.
Abstract: A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.
Abstract: An adaptive temporal motion filter for a video decoder system operates in an infinite impulse response (IIR), a max or a bypass mode. The adaptive temporal motion filter includes an adaptive time constant control module and a filter gain module. A gain factor of the filter gain module is varied by the adaptive time constant control module for every pixel in a current composite video signal. The adaptive time constant control module selects a variable gain for the filter gain module based on the motion magnitude, motion polarity and chroma luma status of the pixel.
Abstract: A street light monitoring system has a small fraction of the street lights in the system being anchor nodes that are configured to detect and store their own actual fixed position, thereby acting as reference points. Further, the other street lights are referred to as blind nodes and do not have their actual fixed position but can derive their position using the coordinates of the anchor nodes and estimating their distance to them. The distance estimation for any blind node can be performed using a received signal strength indication (RSSI) measured at the respective blind node for small distances of up to a threshold value and a link quantization technique takes advantage of the typical placement of the street lights. Inferred distances between the street lights can be assigned to pre-determined categories of distances for a coarse estimation and further position adjustment to a closest possible “real” position.
Abstract: For enhanced interoperability of safety and non-safety communications, a dual-radio type T RSU for improving services includes a first radio dedicated to the control channel and a second radio dedicated to the safety channel. The control channel is divided into a number of synchronous intervals, each about 100 milliseconds in duration. The safety channel is also divided into a number of synchronous intervals, each about 100 milliseconds in duration.
Abstract: A phase lock loop (PLL) circuit incorporates switched capacitive circuitry and feedback circuitry to reduce the time to achieve a lock condition. During a first mode, the frequency of a voltage controlled oscillator (VCO) is used to adjust the control voltage of the VCO to achieve a coarse lock condition. During a second mode, a reference frequency is used to control a charge pump to more precisely adjust the control voltage to achieve fine lock of the PLL. Because the VCO frequency is significantly higher than the reference frequency, the control voltage is varied at a greater rate during the first mode. In some embodiments, the time to achieve lock may be further reduced by initializing the VCO control voltage to a particular voltage so as to reduce the difference between the control voltage at start-up and the control voltage at the beginning of the first mode during coarse lock.
Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
Type:
Application
Filed:
January 17, 2014
Publication date:
May 15, 2014
Applicants:
International Business Machines Corporation, STMicroelectronics, Inc.
Inventors:
John H. Zhang, Yiheng Xu, Carl Radens, Lawrence A. Clevenger
Abstract: A process for manufacturing a packaged microelectromechanical device includes: forming a lid having a face and a cavity open on the face; coating the face of the lid and walls of the cavity with a metal layer containing copper; and coating the metal layer with a protective layer.
Abstract: A first video frame and a second video frame in a flow of digital video frames are encoded by extracting for the frames in question respective sets of keypoints and descriptors, with each descriptor including a plurality of orientation histograms regarding a patch of pixels centred on the respective keypoint. Once a pair of linked descriptors has been identified, one for the first frame and one for the second frame, which have a minimum distance from among the distances between any one of the descriptors of the first frame and any one of the descriptors of the second frame, the differences of the histograms of the descriptors linked in said pair are calculated, and the descriptors linked in said pair are encoded as the set including one of the linked descriptors and the aforesaid histogram differences by subjecting the histogram differences to a thesholding setting at zero all the differences below a certain threshold, to quantization, and to an encoding of a run-length type.
Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.
Abstract: A device for monitoring the temperature surrounding a circuit, including: a charge storage element; a charge evacuation device; and a thermo-mechanical switch connecting the storage element to the evacuation element, the switch being capable of closing without the circuit being electrically powered, when the temperature exceeds a threshold.
Abstract: A control device for controlling a switching power supply adapted to convert an input voltage into an output voltage according to a switching rate of a switching element. The control device includes first control means for switching the switching element in a first working mode at a constant frequency and second control means for switching the switching element in a second working mode at a variable frequency, under a maximum frequency, in response to the detection of a predefined operative condition of the switching power supply. The control device further includes means for selecting the first working mode or the second working mode.
Type:
Application
Filed:
January 16, 2014
Publication date:
May 15, 2014
Applicant:
STMICROELECTRONICS S.r.l.
Inventors:
Giovanni LOMBARDO, Claudio ADRAGNA, Salvatore TUMMINARO
Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.
Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.
Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.
Abstract: An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant regions, arranged at respective depths from the surface of the drift region.
Type:
Application
Filed:
January 23, 2014
Publication date:
May 15, 2014
Applicant:
STMicroelectronics S.r.l.
Inventors:
Davide Giuseppe Patti, Giuditta Settanni