Patents Assigned to STMicroelectronics
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Publication number: 20130163615Abstract: A system comprises a resource, such as an interconnection, for example, of the Network-on-Chip (NoC) type, having an overall bandwidth available for allocation to a set of initiators that compete for allocation of the overall bandwidth. The system includes a communication arbiter for allocating the overall bandwidth to the initiators according to respective values of bandwidth requested (RBW) by the initiators. A control device (50) is configured to detect the deviation between the value of bandwidth allocated to the initiators and the respective value of requested bandwidth and allocate the overall bandwidth to the initiators in a dynamic way minimizing the mean value of the deviation.Type: ApplicationFiled: November 30, 2012Publication date: June 27, 2013Applicants: STMICROELECTRONICS (GRENOBLE2) SAS, STMICROELECTRONICS SRLInventors: STMicroelectronics Srl, STMicroelectronics (Grenoble2) SAS
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Publication number: 20130160518Abstract: A device having an integrated circuit that includes a relative humidity sensor as well as a memory element for storing calibration information for the relative humidity sensor. Because of the nature of fabrication of an integrated circuit for a relative humidity sensor, variances in the creation of electronic components therein may lead to a need to calibrate the sensor after assembly. Such calibration information may be ascertained at the time of fabrication and stored in a memory component disposed on the integrated circuit chip. By storing the calibration information, which may be determined at the time of fabrication, one does not need to determine such calibration information later at assembly or store the already determined calibration information in a remote location until assembly if it was, in fact, ascertained at fabrication. Then, at assembly, one needs only to read the calibration information in order to calibrate the relative humidity sensor.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD.Inventors: Olivier LENEEL, Ravi SHANKAR
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Publication number: 20130164867Abstract: A method of forming an embedded wafer level optical package includes attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier, attaching a dam between two light sensitive sensors of the sensor die, encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer, debonding the carrier, grinding a top surface of the encapsulation layer, forming vias through the encapsulation layer to the sensor die and the LED, filling the vias with conductive material, metalizing the top surface of the encapsulation layer, dielectric coating of the top surface of the encapsulation layer, dielectric coating of a bottom surface of the encapsulation layer, patterning the dielectric coating of the bottom surface of the encapsulation layer, and plating the patterned dielectric coating of the bottom surface of the encapsulation layer.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: STMicroelectronics Pte Ltd.Inventors: Anandan Ramasamy, KahWee Gan, Hk Looi, David Gani
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Patent number: 8470645Abstract: A method for forming a memory cell including a selection transistor and an antifuse transistor, in a technological process adapted to the manufacturing of a first and of a second types of MOS transistors of different gate thicknesses, this method including the steps of: forming the selection transistor according to the steps of manufacturing of the N-channel transistor of the second type; and forming the antifuse transistor essentially according the steps of manufacturing of the N-channel transistor of the first type, by modifying the following step: instead of performing a P-type implantation in the channel region at the same time as in the N-channel transistors of the first type, performing an N-type implantation in the channel region at the same time as in the P-channel transistors of the first type.Type: GrantFiled: March 2, 2011Date of Patent: June 25, 2013Assignee: STMicroelectronics SAInventors: Philippe Candelier, Elise Le Roux
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Patent number: 8472621Abstract: A method for protecting a generation, by an electronic circuit, of at least one prime number by testing the prime character of successive candidate numbers, including: for each candidate number: the calculation of a reference number involving at least one first random number, and at least one primality test based on modular exponentiation calculations; and for a candidate number having successfully passed the primality test: a test of consistency between the candidate number and its reference number.Type: GrantFiled: May 26, 2010Date of Patent: June 25, 2013Assignees: STMicroelectronics (Rousset) SAS, Proton World International N.V.Inventors: Joan Daemen, Frank Cuypers, Gilles Van Assche, Pierre-Yvan Liardet
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Patent number: 8471568Abstract: A method and circuit for evaluating a charge impedance at the output of a directional coupling having a first line adapted to convey a desired signal between a first terminal and a second terminal adapted to be connected to an antenna, and having a second line coupled to the first one including a third terminal on the side of the first terminal and a fourth terminal on the side of the second terminal, wherein the signal present on the fourth terminal is submitted to a homodyne detector having its local oscillator signal sampled from the third terminal.Type: GrantFiled: December 3, 2010Date of Patent: June 25, 2013Assignee: STMicroelectronics (Tours) SASInventors: Sylvain Charley, François Dupont, Benoît Bonnet
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Patent number: 8471370Abstract: A semiconductor element to be mounted on a circuit carrier includes a semiconductor die and at least one lead frame. In order to reduce the size required for mounting a semiconductor die on a circuit carrier, a semiconductor element includes a semiconductor die and at least one lead frame. The at least one lead frame is directly attached to the semiconductor die at a connection region of the semiconductor die, and the connection region provides an electrical connection to and mechanical support for the semiconductor die.Type: GrantFiled: March 23, 2011Date of Patent: June 25, 2013Assignee: STMicroelectronics S.r.l.Inventors: Agatino Carmelo Minotti, Alessandro Lo Piparo
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Patent number: 8471293Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.Type: GrantFiled: January 20, 2009Date of Patent: June 25, 2013Assignee: STMicroelectronics S.r.l.Inventors: Delfo Nunziato Sanfilippo, Emilio Antonio Sciacca, Piero Giorgio Fallica, Salvatore Antonio Lombardo
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Patent number: 8473541Abstract: There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, AX, from the first M-bit argument and a first data bit, BX, from the second M-bit argument, and generates a first conditional carry-out bit, CX(1), and a second conditional carry-out bit, CX(0), wherein the CX(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the CX(0) bit is calculated assuming the row carry-out bit from the second row is a 0.Type: GrantFiled: August 3, 2009Date of Patent: June 25, 2013Assignee: STMicroelectronics, Inc.Inventor: William E. Ballachino
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Patent number: 8471816Abstract: A motion capture device for communicating with a host device in order to input captured motion. The device includes an amplifier module structured to weight displacement measurements by a gain, and an adjustment module structured to adjust the gain as a function of a speed of the capture device.Type: GrantFiled: May 23, 2007Date of Patent: June 25, 2013Assignee: STMicroelectronics SAInventors: Pascal Mellot, Arnaud Glais
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Patent number: 8471505Abstract: A device for the change of the driving mode of an electromagnetic load from a first operating mode with pulse width modulation to a second operating mode that is linear by means of switching circuits. During a first operating mode, each of two outputs has a voltage value ranging from a first reference voltage to a second reference voltage. The device adapted to synchronize a change command signal from a first operating mode to a second operating mode of the electromagnetic load with the signal representative of the flow of current circulating within the load at substantially its average value and adapted to generate a first command signal in response to the synchronization.Type: GrantFiled: March 31, 2010Date of Patent: June 25, 2013Assignee: STMicroelectronics S.r.l.Inventors: Ezio Galbiati, Roberto Peritore, Michele Bartolini, Agostino Mirabelli
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Patent number: 8471557Abstract: Two suspended masses are configured so as to be flowed by respective currents flowing in the magnetometer plane in mutually transversal directions and are capacitively coupled to lower electrodes. Mobile sensing electrodes are carried by the first suspended mass and are capacitively coupled to respective fixed sensing electrodes. The first suspended mass is configured so as to be mobile in a direction transversal to the plane in presence of a magnetic field having a component in a first horizontal direction. The second suspended mass is configured so as to be mobile in a direction transversal to the plane in presence of a magnetic field having a component in a second horizontal direction, and the first suspended mass is configured so as to be mobile in a direction parallel to the plane and transversal to the current flowing in the first suspended mass in presence of a magnetic field having a component in a vertical direction.Type: GrantFiled: December 10, 2010Date of Patent: June 25, 2013Assignee: STMicroelectronics S.r.l.Inventors: Lorenzo Baldo, Francesco Procopio, Sarah Zerbini
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Patent number: 8470283Abstract: A method for growing carbon nanotubes having a determined chirality includes fragmenting at least one initial carbon nanotube having a determined chirality to obtain at least two portions of carbon nanotube. Each portion has a free growth end. Atoms of carbon are supplied with an autocatalyst addition of the atoms of carbon at the free growth end of each portion of nanotube to determine an elongation or growth of the nanotube.Type: GrantFiled: May 3, 2006Date of Patent: June 25, 2013Assignee: STMicroelectronics S.R.L.Inventors: Vincenzo Vinciguerra, Maria Fortuna Bevilacqua, Francesco Buonocore, Salvatore Coffa
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Patent number: 8471299Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.Type: GrantFiled: August 23, 2010Date of Patent: June 25, 2013Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.Inventors: Guo Hua Zhong, Mei Yang
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Patent number: 8471619Abstract: A circuit comprises a frequency divider coupled to receive an oscillating signal generated by an oscillator and a division ratio and configured to divide the oscillating signal by the division ratio into a clock signal; a temperature compensation circuit configured to measure a temperature of the oscillator and generate a division ratio to be provided to the frequency divider and a first value on the basis of the measured temperature; and a control system configured to control connection between a calibration element and the oscillator based on the first value and the oscillating signal of the oscillator.Type: GrantFiled: July 23, 2012Date of Patent: June 25, 2013Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.Inventor: Henry Ge
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Patent number: 8470190Abstract: A method for processing at least one wall of an opening formed in a silicon substrate, successively including the steps of implanting fluorine atoms into an upper portion of the wall of the opening, performing an oxidization step, and applying a specific processing to at least a portion of the non-implanted portion of the opening.Type: GrantFiled: July 16, 2008Date of Patent: June 25, 2013Assignee: STMicroelectronics S.A.Inventors: Edgard Jeanne, Sylvain Nizou
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Patent number: 8471509Abstract: An embodiment of a circuit for maintaining voltage at a voltage bus after a power loss in a hard disk drive system. HDD systems may suddenly lose power and specific tasks, such as parking the read/write head and storing state data may be accomplished using a power generated from back EMF of a motor that is still turning. During the power loss sequence, a drive controller may drive a power chipset to regulate the voltage at a voltage bus so as to conserve power as much as possible. In this manner, the drive circuit may regulate the voltage via a drive algorithm to be just above a threshold voltage (typically 4.4 V) while the HDD system is storing state data, but apply other algorithm for other situations, such as parking the read/write head. Various drive algorithms may be tailored to provide a specific sequence of voltage bus regulation techniques suited to specific applications.Type: GrantFiled: July 20, 2009Date of Patent: June 25, 2013Assignee: STMicroelectronics, Inc.Inventor: Frederic Bonvin
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Patent number: 8470685Abstract: The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing (42) an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing (44) a dielectric liner on the interconnect surface; removing (46) at least part of the dielectric liner on the interconnect surface; successively repeating (48) the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming (50) at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.Type: GrantFiled: January 11, 2007Date of Patent: June 25, 2013Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.Inventors: Joaquin Torres, Laurent-Georges Gosset
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Patent number: 8471962Abstract: Aspects of the invention are directed towards an apparatus and method for detecting local video pixels in mixed cadence video. The local video detector comprises a comb detector that is adaptive to the contour of moving objects and local contrast, a motion detector that is robust to false motion due to vertical details, and a fader value estimator that provides a video confidence value to a fader that combines film mode and video mode processing results. The coupling of the local video detector to a film mode detector increases the robustness, accuracy, and efficiency of local film/video mode processing as compared to the prior art.Type: GrantFiled: June 30, 2011Date of Patent: June 25, 2013Assignee: STMicroelectronics Asia Pacific Pte Ltd.Inventors: Xiaoyun Deng, Lucas Hui
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Patent number: 8472176Abstract: An integrated power adapter system for a portable computer may include a power adapter for providing power to the portable computer, extractable elements for connection to an external socket, and a dissipation grid for reducing the temperature of the cover screen. The power adapter system may be a slim power adapter system being removable from and integrated with the cover screen of the portable computer.Type: GrantFiled: July 18, 2011Date of Patent: June 25, 2013Assignee: STMicroelectronics S.R.L.Inventors: Cristiano Gianluca Stella, Giuseppe Consentino