Abstract: A system and method for adjusting the perceived depth of stereoscopic images are provided. The system includes a disparity estimator, a disparity processor and a warping engine. The disparity estimator is configured to receive a stereoscopic image, to estimate disparities in the stereoscopic image, and to generate an estimator signal comprising the estimated disparities. The disparity processor is configured to receive the estimator signal from the disparity estimator and a depth control signal that is generated based on a user input. The disparity processor is also configured to generate a processor signal based on the estimator signal and the depth control signal. The warping engine is configured to receive the processor signal and to generate an adjusted stereoscopic image by warping the processor signal based on a model.

Abstract: A clamping circuit for a class AB amplifier includes a reference voltage circuit, four NPN Darlington transistors having inputs coupled to the reference voltage circuit, and outputs for providing four clamped voltages, and a split NPN Darlington transistor having an input coupled to the reference voltage circuit, and four separate outputs for providing four AC ground voltages.

Abstract: Display 105 is capable of rendering, or otherwise displaying, one or more of a standard definition (SD) image, a two-dimensional (2D), a three-dimensional image (3D) and a high definition (HD) image 110

Abstract: A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package.

Abstract: An embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has a first submodule node, and the second submodule is disposed over the first submodule and has a second submodule node. The conductive structure couples the first submodule node to one of the module nodes and couples the second submodule node to one of the module nodes. Another embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has first submodule nodes, and the second submodule is disposed over the first submodule and has second submodule nodes. The conductive structure couples one of the first and second submodule nodes to one of the module nodes and couples one of the first submodule nodes to one of the second submodule nodes.

Abstract: A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display.

Abstract: A top-gate molding system for encapsulating semiconductor devices includes a plurality of mold cavities formed between a middle plate and a bottom plate, and a runner system formed between an upper plate and the middle plate. The runner system includes a runner with a plurality of reservoirs along its length, with a gate extending from each of the reservoirs to one of the cavities. A particle trap is positioned on the bottom of the runner between a sprue and a first one of the reservoirs, to capture contaminating particles in a flow of molding compound before the particles enter any of the reservoirs. The particle trap can be, for example, a notch or a channel extending transversely across the bottom of the runner, or a dummy reservoir upstream of the first of the plurality of reservoirs.

Abstract: An electronic device includes a capacitive component with variable capacitance coupled to a control stage that controls the capacitance, based on a reference signal, with a reference frequency, and an excitation signal, that is a multiple of the reference frequency. The capacitive component includes a variable capacitive network having a plurality of switched capacitors, each being switchable between a first configuration, where it is connected between connection terminals of the capacitive component, and a second configuration, where it is connected at most to one of the connection terminals. The control stage includes a logic module, coupled to the variable capacitive network for switching periodically each capacitor between the first configuration and the second configuration. A sign circuit, coupled to the capacitive component supplies a control signal having edges concordant with the excitation signal in one half-period of each cycle of the reference signal and discordant edges in the other half-period.

Abstract: A method of acquiring a satellite signal includes providing a CDMA-modulated signal, defining a first search frequency interval and a first reception sensitivity, and performing a first acquisition of the modulated signal according to the first sensitivity and the first frequency interval in order to provide an acquisition or failed acquisition result. In case of a failed acquisition, performing a second acquisition of the modulated signal as a function of a second search frequency interval, narrower than the first frequency interval, and a second reception sensitivity, greater than the first sensitivity and depending on a power of a side lobe of the modulated signal.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A distributed-line directional coupler including: a first conductive line between first and second ports intended to convey a signal to be transmitted; and a second conductive line, coupled to the first one, between third and fourth ports, the second line being interrupted approximately at its middle, the two intermediary ends being connected to attenuators.

Abstract: A process for electrically testing electronic devices includes connecting at least one electronic device to an automatic testing apparatus suitable for testing digital circuits, and sending, through the apparatus, control signals for electrically testing the electronic device. The process further includes electrically testing the electronic device through at least one reconfigurable digital interface connected to the apparatus through a dedicated digital communication channel and comprising a limited number of communication or connection lines strictly appointed to the exchange of the testing information. Response messages are sent from the electronic device to the apparatus through the digital communication channel in response to the control signals. The response messages contain mesaurements, failure information, and data.

Abstract: An example method for writing and reading data in electrically erasable and programmable nonvolatile memory (EEPROM) cells may include writing, in erased blocks of a first memory zone, data each having a logical address defined in relation to a virtual memory; writing, in a second memory zone, metadata structures associated with the data present in the first memory zone, configuring, in a volatile memory zone, for each logical address of a data stored in the first memory zone, addresses of metadata structures comprising the logical address, reading the look-up table and then reading metadata structures that the look-up table designates, to find, from the logical address of a data, an address in the first memory zone of a block containing a valid data having the logical address.

Abstract: A buffer circuit including an input terminal capable of receiving an input signal and an output terminal capable of being connected to a capacitive load, including an output circuit a series connection, between two terminals of application of a power supply voltage, of a first MOS transistor, a first and a second resistor of adjustable values, and a second MOS transistor, and means for controlling said first and second transistors receiving the input signal The buffer circuit further includes means for comparing the voltage on the output terminal of the circuit with at least one threshold voltage, the comparison means being connected to said control means.

Abstract: An integrated circuit includes a saw-tooth generator including a saw tooth node configured to have a saw-tooth voltage generated thereon; and a first switch having a first end connected to the saw tooth node. The integrated circuit further includes a second switch coupled between an output node and an electrical ground, wherein the first switch and the second switch are configured to operate synchronously. A first current source is connected to the saw tooth node. A second current source is connected to the output node.

Abstract: Processing method for modulated data transmitted in the form of multiplexed frames (Frame 1, . . . Frame 10) containing symbols that have a symbol frequency. The method comprises a frame selection processing operation performed at least partly at a working frequency below the symbol frequency, and a demodulation processing operation comprising at least a part performed at the working frequency on the selected frames.

Abstract: A processor system having a processor core, a plurality of modules connected to the processor core and configured to generate respective fault signals, and a fault managing unit connected to the processor core and to the plurality of modules. The fault managing unit is adapted to collect a first fault signal generated by a first module of the plurality of modules which is in a fault condition, analyze said collected first fault signal, and generate a first reaction signal to be selectively transmitted to said processor core and said first module.

Abstract: A method for searching a digital transmission having unknown carrier and symbol frequencies in a modulated reception signal, includes performing successive trials of several carrier and symbol frequencies, using decreasing values of the symbol frequency, demodulating the reception signal with the tried carrier frequency, filtering the demodulated signal in a band having a width corresponding to the currently tried symbol frequency, and producing samples of the filtered signal. For each currently tried symbol frequency, forming a complex indicator having a real component and an imaginary component established from the successive samples of the filtered signal such that they have cyclostationary properties and that one of the components tends to cancel when the other component tends towards a relative maximum, building the spectrum of the variation of the complex indicator, searching for a singular spike in the spectrum, and determining the real symbol frequency from the frequency of the spike.

Abstract: In a solid state image sensor having a pixel array, a first frame is imaged using varying exposure times in a series of zones. The exposure time for a subsequent frame is selected from the results of the first frame, The exposure times are controlled in a rolling blade manner by controlling the number of lines between reset and readout. The sensor is particularly suited to use in bar code readers.

Abstract: A method of manufacturing a phase change memory (PCM) includes forming a pinch plate layer transversely to a PCM layer that is insulated from the pinch plate layer by a dielectric layer. Biasing the pinch plate layer causes a depletion region to form in the PCM layer. During a read of the PCM in a reset or partial reset state the depletion region increases the resistance of the PCM layer significantly.