Abstract: A method comprises providing a bottom electrode, depositing, on the bottom electrode, an active material comprising a first structural portion having an absorption peak at a UV wavelength, wherein such first structural portion is photo-activatable at such wavelength and which is constituted by monomers or oligomers that, when irradiated at said wavelength, undergo a photo-polymerization and/or photo-cross-linking reaction, or constituted by a polymer that at a UV wavelength undergoes a photo-degradation reaction, and a second electrically active or activatable structural portion which is substantially transparent to such predetermined UV wavelength; exposing a portion of the active material, through a photomask, to UV radiation having such UV wavelength, with photo-activation of the exposed portion of such film; selectively removing either the exposed photo-activated portion or the non-exposed portion, with exposure of a respective portion of the bottom electrode; depositing a head electrode.

Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.

Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3 or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.

Abstract: A semiconductor structure includes a semiconductor substrate, formed on which are a first layer and a second layer, and an alignment-control mask. The alignment-control mask includes a first direction reference element, formed in a first region of the first layer and extending in a first alignment direction, and first position reference elements, formed in a first region of the second layer that corresponds to the first region of the first layer accommodating the first direction reference element. The first position reference elements are arranged in succession in the first alignment direction and in respective staggered positions with respect to a second alignment direction perpendicular to the first alignment direction.

Abstract: An embodiment of a system for physical link adaptation in a wireless communication network such as e.g., a WLAN, selectively varies the physical mode of operation of the transmission channels serving the mobile stations in the network. The system includes an estimation module to evaluate transmission losses due to collisions as well as transmission losses due to channel errors over the transmission channel, and an adaptation module to select the physical mode of operation of the transmission channel as a function of the transmission losses due to collisions and to channel errors as evaluated by the estimation module.

Abstract: A DSC type device manufacturing process includes placing a circuit assembly in a mold. The circuit assembly includes a first heat sink, a semiconductor chip mounted on the first heat sink, a second heat sink mounted on the semiconductor chip and a pin block electrically connected to the semiconductor chip. An outer surface of the first heat sink and an outer surface of the pin block are placed in contact with a first inner surface of the mold. A spacer insert is placed in contact with, and positioned between, a second inner surface of the mold and an outer surface of the second heat sink. The mold is filled with an insulating material that is subsequently hardened. After hardening, a resulting device is extracted from the mold with the outer surfaces of the first heat sink, the pin block and the second heat sink exposed.

Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Abstract: Methods and systems are disclosed for reduced power consumption in communication networks, including sensor networks implemented according to IEEE 802.11ah, by organizing stations into groups having long sleep periods. By organizing the stations of the network into groups, the access point can match each group's traffic identification map with its target beacon transmit time. One embodiment organizes the stations sequentially by AID numbers. Other embodiments organize the stations by similar power save requirements and/or nearby geographical location. Forms of an Extended Traffic Identification Map are matched with an awaken Target Beacon Transmit Time of the group.

Abstract: An optical navigation device, including a radiation source capable of producing a beam of radiation; a sensor for receiving an image; and an optical element for identifying movement of an object on a first surface to thereby enable a control action to be carried out. The optical element is such that a whole of the imaged area of the first surface is substantially covered by the object in normal use. The device is operable to receive from the object on the first surface an input describing a pattern, to compare the received pattern to a stored reference pattern and to perform a predetermined function if the received pattern and stored reference pattern are substantially similar. The pattern may be a continuous line, the device being operable to store the continuous line as a set of turning points in chronological order.

Abstract: A liquid composition is provided for forming a thin film in the form of a mixed composite metal oxide in which a composite oxide B containing copper (Cu) and a composite oxide C containing manganese (Mn) are mixed into a composite metal oxide A represented with the general formula: Ba1-xSrxTiyO3, wherein the molar ratio B/A of the composite oxide B to the composite metal oxide A is within the range of 0.002<B/A<0.05, and the molar ratio C/A of the composite oxide C to the composite metal oxide A is within the range of 0.002<C/A<0.03.

Abstract: An integrated circuit includes an integrated transformer of the balanced-to-unbalanced type with N channels, wherein N is greater than 2. The integrated transformer includes, on a substrate, N inductive circuits that are mutually inductively coupled, and respectively associated with N channels.

Abstract: Methods and systems are disclosed specifying the arrangement and content of the fields in data and management frames, which allow for greater payload efficiency in frame-based communication networks. The content of the fields is changed from the standard 802.11 arrangement to meet of the needs of networks such as Sub-1GHz networks, including those of the 802.11 ah standard, and sensor networks with a large number of stations transmitting at low data rates. In some embodiments, MAC header fields are reduced from standard 802.11 header fields by using only two fields for addressing and eliminating standard fields that are not used in sensor networks.

Abstract: A pixel readout circuit including at least first, second and third memory locations. During an integration period of a pixel, the pixel readout circuit repeatedly samples the pixel output level during the integration period, stores the first sample in the first memory location, and stores each subsequent sample in memory locations other than the first memory location. Each sample is stored with a time corresponding to when that sample was taken, such that at any one time subsequent to the first three samples having been stored, at least the first sample and the two most recent samples are stored. Also disclosed is a corresponding method of reading out of a pixel output over an undefined integration period.

Abstract: A method may include a cycle of reading a current pixel including connecting the capacitive node of the pixel to a capacitive node of a previous pixel already read, connecting the capacitive node of the current pixel and the capacitive node of a previous pixel to an output line, reading a first voltage of the capacitive node of the pixel through the output line, transferring charges from the accumulation node to the capacitive node of the pixel, reading a second voltage of the capacitive node of the pixel through the output line, and disconnecting the capacitive node from the capacitive node of a previous pixel, and a cycle of reading a next pixel. This cycle may include accumulating charges in the accumulation node of the next pixel while the capacitive node of the current pixel is connected to a capacitive node of a previous pixel.

Abstract: The present disclosure is directed to a voltage-to-current sensing circuit having a bias terminal configured to receive a reference voltage, an offset terminal configured to receive an offset current, and an operational amplifier configured to output a low voltage signal. The device includes a first amplifier having first and second high voltage inputs configured to receive a first voltage difference across a sense component on a high voltage line and to generate a first current, a second amplifier having first and second low voltage inputs configured to receive a second voltage difference between the bias terminal and the offset terminal and to generate a second current, a summing circuit configured to provide an intermediate voltage corresponding to a sum of the first and the second currents, and a low-voltage transistor coupled to an output of the amplifier and controlled by the intermediate voltage to generate the output current.

Abstract: A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.

Abstract: An electronic component package includes a support and heat conductor. The heat conductor has a protuberance and the support has a socket arranged to be able to receive the protuberance so that the movement of heat conductor relative to the support during the assembly process is reduced.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: A power bipolar structure is described having at least one first, one second and one third terminal and including at least one power bipolar transistor having a finger structure coupled to at least one driving block. The power bipolar transistor includes at least one elemental bipolar cell connected to these first, second and third terminals and including at least one power elemental bipolar structure corresponding to a finger of the power bipolar transistor, electrically coupled between the first and second terminals and coupled to a driving section of the driving block by at least one sensing section able to detect information on the operation of the power elemental bipolar structure, the sensing section being in turn coupled to a control circuit and supplying it with a current value as a function of the local temperature of the power elemental bipolar structure.

Abstract: A digital imaging sensor includes an array of pixels. A subset of the pixels in the array has reduced photosensitivity in comparison to other pixels in said array. A controller operates to control an integration time of the array of pixels such that a first integration time of the subset of pixels is longer than a second integration time of the other pixels in the array. Such an image sensor is particularly useful for sensing light sources that are not illuminated continuously.