Abstract: The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.

Abstract: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.

Abstract: The present disclosure is directed to a device and a method for achieving a precise capacitance of a capacitor. The method includes trimming a first capacitance of the capacitor to a second capacitance, the capacitor having a first conductive layer separated from a second conductive layer by a dielectric layer. Changing a first dielectric constant of the dielectric layer to a second dielectric constant, where the first dielectric constant corresponding to the first capacitance and the second dielectric constant corresponding to the second dielectric constant includes heating the dielectric layer above a threshold temperature for a time period. The heat is provided by either one of the plates of the capacitor or from a separate heater.

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 ?m, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract: A voltage controlled variable resistor circuit is configured to variably attenuate a variable source signal. A fixed attenuation circuit is coupled to receive the variable source signal and output an attenuated variable source signal. The variable source signal is further applied across a variable resistive divider formed of a fixed resistive circuit and a variable resistive circuit. The variable resistive circuit has a first input configured to receive the attenuated variable source signal and a second input configured to receive a variable resistance control signal. The variable resistive circuit is configured to have a resistance which is variable in response to the attenuated variable source signal and the variable resistance control signal.

Abstract: A device includes a positive power supply voltage node; and a first operational amplifier including a first input, a second input, and an output coupled to the second input. The device further includes a first resistor coupled between the second input of the first operational amplifier and the positive power supply voltage node; a second resistor coupled between the output of the first operational amplifier and an electrical ground, and is configured to receive a same current flowing through the first resistor; a second operational amplifier including a first input coupled to the second resistor, and an output coupled to an output node; and a third resistor coupled between the electrical ground and a second input of the second operational amplifier.

Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract: A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A capacitive humidity sensor includes a first electrode, a humidity sensitive dielectric layer, and a second electrode. The humidity sensitive dielectric layer is between the first and the second electrodes. The humidity sensitive dielectric layer is etched at selected regions to form hollow regions between the first and second electrodes.

Abstract: A method distributes personalized circuits to one or more parties. The method distributes a generic circuit to each party, encrypts a unique personalization value using a secret encryption key, and transmits each encrypted personalization value to the corresponding party. Each party then stores the encrypted personalization value in their circuit. The stored encrypted personalization value allows a piece of software to be properly executed by the circuit. A semiconductor integrated circuit is arranged to execute a piece of software that inputs a personalization value as an input parameter. The circuit comprises a personalization memory arranged to store an encrypted personalization value; a key memory for storing a decryption key; a control unit comprising a cryptographic circuit arranged to decrypt the encrypted personalization value using the decryption key; and a processor arranged to receive the decrypted personalization value and execute the software using the decrypted personalization value.

Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.

Abstract: A system includes a device of the surface-mounting type having an insulating package provided with a mounting surface and a contact pin exposed on the mounting surface. The device is attached to an insulating board including a gluing surface and an opposite surface. The process for manufacturing the system includes forming through holes a contact region on the gluing surface. The mounting surface is glued to the gluing surface with the contact pin aligned with the contact region. Wave soldering is performed to electrically join the device to the board by hitting the opposite surface with a wave of soldering paste to form, by capillary action with the soldering paste ascending in the through holes up to the overflow on the gluing surface, a conductive contact electrically connecting the contact pin of the electronic device through a solder connection to the contact region of the electronic board.

Abstract: A resonant device including a stack of a first metal layer, a piezoelectric material layer, and a second metal layer formed on a silicon substrate, a cavity being formed in depth in the substrate, the thickness of the silicon above the cavity having at least a first value in a first region located opposite to the center of the stack, having a second value in a second region located under the periphery of the stack and having at least a third value in a third region surrounding the second region, the second value being greater than the first and the third values.

Abstract: The method is for managing operation of a first apparatus belonging to a first communication system and exchanging within the first communication system a multi-carrier modulated signal on several sub-carriers. The method includes detecting at the first apparatus the presence of an interfering signal emitted from a victim apparatus on a sub-carrier. The method may also include determining at the first apparatus the path loss between both apparatuses, determining from the path loss and from an allowed interference level at the victim apparatus a maximum allowed transmit power on the sub-carrier of a multi-carrier modulated signal to be transmitted from the first apparatus, and adjusting within the first apparatus the processing of the multi-carrier modulated signal to be transmitted in accordance with the maximum allowed transmit power.

Abstract: A method of processing a digital image which includes at least one contour zone, including a contour zone sharpness processing. The sharpness processing includes a conversion of the cues regarding level of pixels of the contour zone into initial main cues, lying between zero and a main value dependent on the amplitude of the contour, a sharpness sub-processing performed on these initial main cues so as to obtain final main cues, and a conversion of the final main cues into final cues regarding levels.

Abstract: A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.

Abstract: A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion.

Abstract: An embodiment of an integrated circuit design framework comprises a user interface which automatically initializes a three-dimensional simulation tool for simulating or analyzing the characteristics of a complex metallization system. In some illustrative embodiments the user interface may additionally provide electrically simulated parameter values for an input parameter, such as the channel resistance of a power transistor, thereby enabling a simulation of a portion of interest of the metallization system without actually requiring the provision of the design data of the power transistor.