Abstract: An image processing system includes an image reconstruction unit. The image reconstruction unit is configured to receive an image at a first resolution, apply the image to a look-up table and output a version of the image at a second resolution. The second resolution includes a higher resolution than the first resolution. In addition, the look-up table is generated inputting a plurality of training images; classifying, into a number of classes, a plurality of images patches corresponding to each of the plurality of training images; re-classifying the number of classes into a final class; and synthesizing filters corresponding to each of the class into a final filter value.

Abstract: A magnetic field sensor, including a Hall magnetic sensor, formed within a first die and configured to detect a first magnetic field, and a first anisotropic magnetoresistive magnetic sensor, having a first anisotropic magnetoresistive transducer, formed within a second die and configured to generate an electrical measurement quantity as a function of a second magnetic field. An electronic reading circuit formed within the first die, is electrically connected to the first anisotropic magnetoresistive transducer, and provides a first measure indicating the second magnetic field, on the basis of the electrical measurement quantity. The first and second dice are fixed with respect to one another and have main surfaces parallel to the same reference plane. The first magnetic field being oriented in a first direction perpendicular to the reference plane and the second magnetic field being oriented in a second direction parallel to the reference plane.

Abstract: Solder joint reliability in an integrated circuit package is improved. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.

Abstract: A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.

Abstract: A method of controlling a pulse width modulated (PWM) voltage regulator including a control circuit of a power stage, and a circuit configured to determine a duration of charge phases and further configured to receive a charge signal and to generate a logic command may include controlling, using the control circuit, switches of the power stage as a function of the logic command at an end of a charge phase and at a start of a discharge phase of an output capacitance. The method may also include generating the charge signal to be one of enabled and disabled during charge phases and another of enabled and disabled during discharge phases, and delaying, at each PWM cycle, the logic command with respect to a previous PWM cycle to compensate at least one of a phase and a frequency difference between each PWM cycle and a reference clock signal.

Abstract: An integrated circuit including a semiconductor layer; and a MOS transistor including first and second power terminals and a bulk insulated from the semiconductor layer, the first power terminal being intended to receive an oscillating signal, the transistor gate and the bulk being connected to the first power terminal.

Abstract: An image processing device including an encoder processor and a decoder circuit. The encoder processor receives image data from a sensor and encodes the data with padding data if a series of bytes indicative of command sequence occur within the image data. The decoder circuit receives the image data and the padding data, and removes the padding data from within the image data.

Abstract: An embodiment of an electronic device having a plurality of operative parameters is provided. The electronic device includes means for applying a plurality of trimming actions to each parameter for causing a corresponding correction of the parameter, for at least one reference parameter, means for measuring the reference parameter responsive to the application of at least part of the trimming actions, and means for forcing the application of the selected trimming action for the reference parameter. For each non-reference parameter different from the at least one reference parameter, the electronic device includes means for selecting one of the trimming actions for the non-reference parameter corresponding to the selected trimming action for the at least one reference parameter, and means for forcing the application of the selected trimming action for each non-reference parameter.

Abstract: A method of authentication of a terminal generating a magnetic field, by a transponder including an oscillating circuit from which a D.C. voltage is generated, wherein the transponder: receives first data relative to the current in an oscillating circuit of the terminal, measured by the terminal for a first value of the resistive load of the transponder; and exploits these first data and second data relative to the level of said D.C. voltage, respectively measured for the first resistive load value and for a second resistive load value.

Abstract: A method of estimating log-likelihood ratios for first and second streams of samples of a received S-FSK signal demodulated using first and second carriers includes estimating channel and noise parameters associated with first and second transmitted values for the first and second streams of samples obtained from the received S-FSK modulated signal. Current signal-to-noise ratios are estimated for current samples of the first and second streams of samples obtained from the received S-FSK modulated signal using the channel and noise parameters. The estimated current signal-to-noise ratios are compared with values of a discrete ordered set and respective pairs of consecutive values of the discrete ordered set between which the estimated current signal-to-noise ratios are comprised are identified. Log-likelihood ratios are estimated for the current samples of the first and second streams.

Abstract: In accordance with an embodiment, a network device includes a network controller and at least one network interface coupled to the network controller that includes at least one media access control (MAC) device configured to be coupled to at least one physical layer interface (PHY). The network controller may be configured to determine a network path comprising the at least one network interface that has a lowest power consumption of available media types coupled to the at least one PHY.

Abstract: An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically connected together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes.

Abstract: A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

Abstract: A method of testing integrated circuits, including establishing at least a first physical communication channel between a test equipment and an integrated circuit under test by having at least a first probe of the test equipment contacting a corresponding physical contact terminal of the integrated circuit under test; having the test equipment and the integrated circuit under test exchange, over said first physical communication channel, at least two signals selected from the group including at least two test stimuli and at least two test response signals, wherein said at least two signals are exchanged by means of at least one modulated carrier wave modulated by the at least two signals.

Abstract: A battery pack management system provides information such as remaining capacity and/or run time to empty for a battery. A time taken for a battery voltage to drop a threshold amount is measured and used to determine a remaining capacity of the battery. The time may be associated with a temperature and current of the battery. The remaining capacity of a battery is calculated by monitoring a discharge of the battery. For example, current drawn from the battery is monitored over a period of time and an initial amount by which the battery has been discharged is calculated. Compensation of this initial amount is carried out in order to take into account factors such as temperature, self-discharge rate and age of the battery.

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract: A video window detector includes a region characteristic determiner to generate at least one characteristic value for at least one region of a display output; a characteristic map generator to generate an image map from the at least one characteristic value for at least one region of the display output; and a window detector to detect at least one video window dependent on the image map.

Abstract: Disclosed herein is a microfluidic jetting device having a piezoelectric member positioned above a displaceable membrane. A voltage is applied across the piezoelectric member causing deformation of the piezoelectric member. The deformation of the piezoelectric member results in a displacement of the membrane, which is formed above a cavity. Displacement of the membrane creates pressure to jet or eject liquid from the cavity and suction liquid into the cavity through ports or apertures formed in the in membrane.

Abstract: A MEMS gyroscope includes: a microstructure having a fixed structure, a driving mass, movable with respect to the fixed structure according to a driving axis, and a sensing mass, mechanically coupled to the driving mass so as to be drawn in motion according to the driving axis and movable with respect to the driving mass according to a sensing axis, in response to rotations of the microstructure; and a driving device, for keeping the driving mass in oscillation with a driving frequency. The driving device includes a discrete-time sensing interface, for detecting a position of the driving mass with respect to the driving axis and a control stage for controlling the driving frequency on the basis of the position of the driving mass.

Abstract: An antenna circuit for a device of transmission/reception by inductive coupling, including a first inductive element in parallel with a capacitive element and, between each node of the parallel association and two terminals of a switch, a second inductive element.