Abstract: A method for rendering a three dimensional scene on a displaying screen comprises: generating for a tile of a current scene a hierarchical z-buffer which comprises a plurality of levels organized according to depth values; calculating a minimum depth value d of a submitted primitive; calculating an intersection area associated with said primitive with respect to said tile; providing a multiplicity of aligned regions each associated with a level of the hierarchical z-buffer so that the exact area calculated is suitable to be covered, at least entirely, by the union of such aligned regions; comparing the minimum depth value d of the submitted primitive with corresponding maximum depth values v1, v2, . . . , vN each read from the levels of the hierarchical z-buffer; discarding said primitive whether the minimum depth value d is bigger than all maximum depth values v1, v2, . . . , vN.

Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.

Abstract: A receiver for receiving a data stream comprises a filtering arrangement for filtering said received data stream and a processor. The filtering arrangement is arranged to load at least a part of said data stream, to filter at least part of said data stream and to read at least part of said data stream. The filtering arrangement has a first mode in which said steps are carried out and a second mode in which said processor is arranged to interrupt the steps carried out by said filtering arrangement.

Abstract: An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

Abstract: A camera is mounted in a sphere-shaped housing. The housing can be rotated within a base that permits the camera to take multiple images covering a panoramic view. Motion of the housing within the base is detected by motion sensors that provide positional information for allowing the images to be stitched together. The motion sensors are optical mice sensors. Processing circuitry and a power supply may be located within the housing.

Abstract: In this invention, a new class of finite precision multilevel decoders for low-density parity-check (LDPC) codes is presented. These decoders are much lower in complexity compared to the standard belief propagation (BP) decoder. Messages utilized by these decoders are quantized to certain levels based on the number of bits allowed for representation in hardware. A message update function specifically defined as part of the invention, is used to determine the outgoing message at the variable node, and the simple min operation along with modulo 2 sum of signs is used at the check node. A general methodology is provided to obtain the multilevel decoders, which is based on reducing failures due to trapping sets and improving the guaranteed error-correction capability of a code. Hence these decoders improve the iterative decoding process on finite length graphs and have the potential to outperform the standard floating-point BP decoder in the error floor region.

Abstract: A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.

Abstract: An optical component focus testing apparatus includes a plurality of test pattern displays. One or more illuminators are configured to selectively illuminate different test pattern displays at different times. Light directors are provided to direct light from at least one of the illuminated test pattern displays towards an optical component under test. The light directors and test pattern displays are arranged such that, in use, light directed from different illuminated test pattern displays travel different distances to reach the optical component under test.

Abstract: A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.

Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Abstract: A method of processing digital images by transforming a set of pixels from a three-dimensional space to a normalized two-dimensional space, determining a membership class and membership class level of each pixel in the set of pixels, and selectively modifying colors of pixels in the set of pixels based on the determined membership classes and membership class levels.

Abstract: A data transmission device includes a coder configured to code the data into a multifrequency signal. A first array of ultrasonic transducers with a vibrating membrane is disposed on a first surface of a wafer. The first array configured to convert the signal into a multifrequency acoustic signal propagating in the wafer. A second array of ultrasonic transducers is disposed on a second surface of the wafer. The second array includes at least two assemblies of vibrating membrane ultrasonic transducers having resonance frequencies equal to two different frequencies of the multifrequency signal.

Abstract: An oscillator device includes: a structural layer extending over a first side of a semiconductor substrate; a semiconductor cap set on the structural layer; a coupling region extending between and hermetically sealing the structural layer and the cap and forming a cavity within the oscillator device; first and second conductive paths extending between the substrate and the structural layer; first and second conductive pads housed in the cavity and electrically coupled to first terminal portions of the first and second conductive paths by first and second connection regions, respectively, which extend through and are insulated from the structural layer; a piezoelectric resonator having first and second ends electrically coupled, respectively, to the first and second conductive pads, and extending in the cavity; and third and fourth conductive pads positioned outside the cavity and electrically coupled to second terminal portions of the first and second conductive paths.

Abstract: A process for manufacturing a membrane of nozzles of a spray device, comprising the steps of laying a substrate, forming a membrane layer on the substrate, forming a plurality of nozzles in the membrane layer, forming a plurality of supply channels in the substrate, each supply channel being substantially aligned in a vertical direction to a respective nozzle of the plurality of nozzles and in direct communication with the respective nozzle.

Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

Abstract: A method for protecting a key used, by an electronic circuit, in a symmetrical algorithm for ciphering or deciphering a message, including the steps of complementing to one the key and the message; executing the algorithm twice, respectively with the key and the message and with the key and the message complemented to one, the selection between that of the executions which processes the key and the message and that which processes the key and the message complemented to one being random; and checking the consistency between the two executions.

Abstract: An embodiment of a method and system are provided for managing both system resources and power consumption of a computer system, involving different layers of the system: an application layer, a middle layer where the operating system is running and where a power manager is provided, and a hardware layer used for communicating with the hardware devices. Hardware devices have different operating modes which provide distinct trade-offs between performances and power consumption. Performance requirements defined at the level of the application layer, as well as the device power status of the system, set constraints on the system resources. The middle layer power manager may be in charge of retrieving performance requirements in form of constraints set on system parameters, aggregating these constraints opportunely and communicating corresponding information to the device drivers which may then select a best operating mode.

Abstract: An area efficient system that includes a first circuit to synchronize a clock signal and a data signal and a data retaining and processing device to receive data from said data bus to thereby generate a status signal indicating the receipt of data by said area efficient system; a reference bus address and said data bus. The system also includes a device to compare the reference bus address with the content of memory for generating an address matching signal and a control signal generator to govern the data write signal generation for said shifting means. The system further includes a sequencer to read and write data from/to said data retaining and processing device in a plurality of subcycles for efficiently accessing storage buffers and a direct storage access controlling means for generating interrupt signals and access request signals.