Abstract: An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon.

Abstract: A current reuse device including a first stage provided with a first input for a first input signal and a first output for a first output signal; a second stage comprising a second input for a second input signal and a direct current terminal operating as a ground terminal for alternate signals; a first inductor connected to a first output and to the direct current terminal so that the first and second stages share a direct current; a second inductor reciprocally coupled to the first inductor and connected to the second input in order to generate the second input signal as a function of the first output signal.

Abstract: A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer.

Abstract: An NFC controller analyzes incoming commands, by name, and decides, according a predefined name table, to which secure element the actual command and following commands are sent for processing.

Abstract: An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side.

Abstract: An embodiment concerns a method for encrypting a message through a cryptographic algorithm including a computation of a mathematical function including the computation of one or more modular multiplications. Such a cryptographic algorithm has a respective module. The method, carried out with an electronic device, includes: providing a first parameter; generating a random number; calculating a Montgomery parameter based on said first parameter and on a integer multiple of said random number; generating a representation of the message to be encrypted in a Montgomery domain through a Montgomery conversion function applied to the message and to the Montgomery parameter; carrying out the calculation of the mathematical function on the message represented in the Montgomery domain.

Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.

Abstract: A polymeric layer encompassing the solder elements of a ball grid array in an electronics package. The polymeric layer reinforces the solder bond at the solder ball-component interface by encasing the elements of the ball grid array in a rigid polymer layer that is adhered to the package structure. Stress applied to the package through the ball grid array is transmitted to the package structure through the polymeric layer, bypassing the solder joint and improving mechanical and electrical circuit reliability. In one embodiment of a method for making the polymeric layer, solder elements bonded to external pads on a structure of the package are submerged in a fluidic form of the polymeric layer. The fluidic form is solidified and then a portion of the resulting polymeric layer is removed to make the solder elements accessible for mounting the package to a printed circuit board or other external circuit.

Abstract: The present disclosure is directed to a thin film resistor having a first resistor layer having a first temperature coefficient of resistance and a second resistor layer on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 50 and 150 angstroms and the second resistor layer may have a thickness in the range of 20 and 50 angstroms.

Abstract: An optical image stabilization (OIS) system may be used in a camera having an optical system which includes a motion compensating optical element driven by an actuator. The system may include a motion sensor providing a motion signal, a frequency detector for detecting a dominant frequency being that frequency within the motion signal which may produce the most significant motion blurring in the image produced by the camera, and a tunable high-pass filter for filtering the motion signal and supplying the filtered motion signal as an actuator control signal. The tunable high pass filter may be tuned based upon the dominant frequency to a filter characteristic which provides a phase lead substantially canceling a phase lag of the actuator at that frequency.

Abstract: Transmission of multicast packets over a local area network is controlled by: identifying the condition where only a single receiver exists within the local area network for a given multicast group of packets, and allowing, upon occurrence of that condition, Automatic Repeat Request of the packets multicast towards said single receiver. A preferred field of application is wireless local area networks for use in a home environment.

Abstract: A cross-point cell nanoarray comprises a mechanical support substrate, first and second orders of uniformly spaced parallel electrodes separated by an electrically active organic film and orthogonally arranged to form an array of cross-point cells, individually addressable by biasing the respective opposite electrodes, by selecting them among those of the respective orders, over a planar area of the substrate. The active organic resin layer includes a block copolymer of a major component resin and of at least one different minor component resin, configured to promote formation of large-scale ordered nanostructures through phase segregation, due to block incompatibility and self-assembly properties of the blocks. Polymeric bocks of the ordered nanostructures configured to sequester conductive nanoparticles and/or conductive nanoparticle clusters originally dispersed in the component organic resins, subtracting them from the surrounding matrix copolymer.

Abstract: Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.

Abstract: A boost circuit is used for power factor correction (PFC). In a low power application, transition mode control is utilized. However, switching frequency varies with different input voltages, and over a wide input voltage range, the switching frequency can become too high to be practical. To address this issue, a boost circuit is provided whose effective inductance changes as a function of input voltage. By changing the inductance, control is exercised over switching frequency.

Abstract: A method of controlling an output voltage of a pulse width modulation (PWM) converter with a PWM signal driving a power switch of the converter may include using a comparator to compare a reference voltage with a scaled output voltage of the converter, incrementing or decrementing an up/down counter at each pulse of a clock signal applied to the counter depending on a state of the comparator, and controlling the comparator to generate the PWM signal with a control voltage selected from a look-up table using a value of the counter.

Abstract: A MEMS detection structure is provided with: a substrate having a top surface, on which a first fixed-electrode arrangement is set; a sensing mass, extending in a plane and suspended above the substrate and above the first fixed-electrode arrangement at a separation distance; and connection elastic elements that support the sensing mass so that it is free to rotate out of the plane about an axis of rotation, modifying the separation distance, as a function of a quantity to be detected along an axis orthogonal to the plane. The MEMS detection structure also includes: a coupling mass, suspended above the substrate and connected to the sensing mass via the connection elastic elements; and an anchoring arrangement, which anchors the coupling mass to the substrate with a first point of constraint, set at a distance from the axis of rotation and in a position corresponding to the first fixed-electrode arrangement.

Abstract: Radio frequency (RF) architectures for spectrum access networks are provided. Embodiments of the invention generally provide a radio frequency (RF) architecture for customer premise equipment (CPE) for use in, for example, IEEE 802.22 wireless regional area networks (WRANs). In some embodiments, the CPE RF architecture includes two receive chains with a directional antenna and an omni-directional antenna, respectively. The CPE RF architecture facilitates opportunistic out-of-band spectrum sensing and WRAN signal receiving that are performed in parallel with data transmission.

Abstract: An integrated power MOSFET device formed by a substrate); an epitaxial layer of N type; a sinker region of P type, extending through the epitaxial layer from the top surface and in electrical contact with the substrate; a body region, of P type, extending within the sinker region from the top surface; a source region, of N type, extending within the body region from the top surface, the source region delimiting a channel region; a gate region; a source contact, electrically connected to the body region and to the source region; a drain contact, electrically connected to the epitaxial layer; and a source metallization region, extending over the rear surface and electrically connected to the substrate and to the sinker region.

Abstract: Contention based period beamforming includes the establishment of synchronized communications between a beamforming initiator and a beamforming responder to precisely define a start time for beamforming training. Synchronization between the beamforming initiator and beamforming responder begins with the sending of control information to the responder so that the start of the beamforming process will be synchronized. With beamforming training synchronized, beamforming is initiated using the sector sweep process.

Abstract: A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.