INTERACTION STRUCTURE FOR A STORAGE MEDIUM

Abstract

A process manufactures an interaction structure for a storage medium. The process includes forming a first interaction head provided with a first conductive region having a sub-lithographic dimension. The step of forming a first interaction head includes: forming on a surface a first delimitation region having a side wall; depositing a conductive portion having a deposition thickness substantially matching the sub-lithographic dimension on the side wall; and then defining the conductive portion. The sub-lithographic dimension preferably is between 1 and 50 nm, more preferably 20 nm.

Description

BACKGROUND

1. Technical Field

The present invention relates to a process for manufacturing an interaction structure for a storage medium, in particular for “probe storage” applications, to which the ensuing treatment will make explicit reference without, however, this implying any loss of generality.

2. Description of the Related Art

As is known, storage systems using a magnetism-based technology, such as, for example, hard disks, suffer from major limitations as regards the increase in data-storage capacity, the read/write speed, and size reduction. In particular, a physical limit exists, referred to as “superparamagnetic limit”, which hinders reduction in the dimensions of the magnetic-storage domains below a critical threshold without running the risk of losing the stored information.

In the last few years alternative storage systems have consequently been proposed, amongst which the so-called “probe storage” systems (referred to also as “atomic storage” systems) have assumed particular importance. These systems enable high data-storage capacities to be achieved with small overall dimensions and with low manufacturing costs.

In brief (see FIG. 1), a “probe storage” device comprises a two-dimensional array of transducers (or probes) 2 fixed to a common substrate 3, made, for example, of silicon, arranged above a storage medium 4 and movable with respect to the storage medium, generally in two orthogonal directions, due to the action of a micromotor associated therewith. Each transducer 2 is provided with a supporting element 5 made of semiconductor material, in particular silicon, generally known as “cantilever”, which is suspended in cantilever fashion above the storage medium 4 and carries at one free end an interaction structure 6 (referred to also as “sensor structure” or “contact structure”) facing the storage medium 4. In particular, by the term “interaction” is meant herein any operation of reading, writing or erasure that implies an exchange of signals between the interaction structure and the storage medium. Via the respective interaction structure 6, each transducer 2 is able to interact locally with a portion of the storage medium, for reading/writing/erasing individual bits of information.

The physical characteristics (hardness, roughness, etc.), morphological characteristics (dimensions, shape, etc.), and electrical characteristics (resistivity, thermal conductivity, etc.) of the interaction structure 6 are strictly correlated to the material of the storage medium with which they are associated (polymeric material, ferroelectric material, phase-change material, etc.), and to the mechanisms of interaction for reading/writing/erasing of data (thermal process, passage of charge, etc.).

For example, in some storage systems of the “probe storage” type reading/writing of the individual bits is carried out by interacting with the storage material via a passage of electrical charges through the interaction structure. In particular, in the case where ferroelectric storage media are used, the read operations are destructive, i.e., they imply removal of the stored information and the impossibility for carrying out any subsequent reading of the same data. In fact, reading of a portion of the memory (or trace) corresponds to writing in said portion of memory a sequence of charges that are all positive (or all negative, according to the polarization of an interaction structure). Consequently, during reading, the flow of the read data is stored in a memory buffer, the dimensions of which are at least the same as the dimensions of the trace that is being read. In addition, the contents of the memory buffer are subsequently re-written on the previously read trace, so that the interaction structure is re-positioned at the beginning of the trace, re-writes the entire trace, and subsequently can start a new read operation.

BRIEF SUMMARY

One embodiment is a manufacturing process that enables the aforesaid problems and disadvantages to be overcome, and in particular that enables definition of an interaction head of nanometric dimensions without resorting to the use of a purely lithographic process.

A process for manufacturing an interaction structure for a storage medium is provided, as defined in claim 1.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached plate of drawings, wherein:

FIG. 1 is a partially exploded schematic perspective representation of a probe-storage device;

FIGS. 2-10 show perspective sections of a wafer of semiconductor material on insulator in successive steps of a manufacturing process according to a first embodiment of the present invention; and

FIGS. 11-13 show perspective sections of the wafer of semiconductor material in final steps of a manufacturing process according to a second embodiment of the present invention.

DETAILED DESCRIPTION

In order to solve the problem of re-writing after a destructive read, in the U.S. Pat. No. 8,031,579 assigned to the assignee of the present application, the use has been proposed of an interaction structure 6 comprising two adjacent interaction heads (designated by 7 and 8 in FIG. 1) aligned with respect to one another in a scanning direction, which move in line in one and the same scanning direction with respect to the storage medium. A first interaction head 7 is a read head, which reads the data stored in a given position and consequently erases them, whereas a second interaction head 8 is a write head, which follows the read head and restores and re-writes the data previously erased.

The process for manufacturing a probe-storage device envisages, in a known way, the formation of the array of transducers 2 on a silicon-on-insulator (SOI) wafer, using MEMS microfabrication techniques enabling the release of the various cantilever supporting elements from an epitaxial layer of the SOI wafer. Up to now, completely satisfactory processes for manufacturing the interaction structures 6 associated to the various transducers 2 have not, however, been proposed. In addition, the manufacturing processes of a known type do not envisage fabrication of a number of interaction heads integrated on a same supporting element.

In particular, since the distance between the ferroelectric domains, and hence between subsequent bits stored on the storage medium (referred to also as “bit pitch”), can reach values of the order of some tens of nanometers, in order to obtain devices with high capacities, the interaction heads have at least one dimension compatible with said distance, so that also this dimension can be in the order of some tens of nanometers (for example, 20 nm). Consequently, traditional lithographic techniques prove inadequate for providing these heads, or involve, in any case, considerable costs for their fabrication (in the case where the dimensions, though still compatible with the lithographic limits, require use of costly apparatuses to achieve a lithographic definition of less than 100 nm).

As will be described in detail hereinafter, one embodiment envisages definition of a sub-lithographic dimension of an interaction structure for a storage medium (which is once again designated by the reference number 6, as in FIG. 1), via a non-lithographic process, in particular, via deposition of one or more layers having appropriate thicknesses. Current deposition techniques enable, in fact, formation of very thin layers (having sub-lithographic thicknesses), which can be controlled with extreme precision. It should be noted that the expression “sub-lithographic dimension” is used herein to indicate a dimension smaller than a minimum dimension obtained with a lithographic technique; for example, a sub-lithographic dimension is smaller than 50 nm. In one embodiment, the sub-lithographic dimension is approximately 20 nm.

The process for manufacturing an interaction structure 6 for interaction with a storage medium 4 according to a first embodiment of the present invention envisages (FIG. 2) formation of a wafer of semiconductor material on insulator (SOI wafer) 11, comprising a substrate 12 (which is not shown in the subsequent figures), for example made of silicon, a buried-oxide layer 13 (which is not shown in the subsequent figures either), and an epitaxial layer 14, for example made of silicon. In particular, in a per-se known manner, within the epitaxial layer 14 a supporting element 5 for the interaction structure 6 will be formed, and the thicknesses of the epitaxial layer 14 and of the buried-oxide layer 13 are consequently chosen according to the mechanical and electrical specifications that the supporting element must meet (in terms of resistivity, stiffness, etc.). For example, the epitaxial layer 14 has a thickness of 2-10 μm, and the buried-oxide layer 13 has a thickness of 0.5-2 μm.

Next, a first insulating layer (not shown), for example made of silicon oxide or silicon nitride, is deposited on the epitaxial layer 14. The material of the first insulating layer should be compatible, in a known way, with a subsequent process of definition of the supporting element carrying the interaction structure, and of its release from the epitaxial layer 14. The first insulating layer is then defined via a dry etch through a purposely provided etching mask (not illustrated) so as to leave an insulation region 15 (FIG. 3) thereof, for example, having a rectangular section with non-critical dimensions (e.g., 5×50 μm). The insulation region 15 has a top wall 15a and side walls 15b, and defines a step having a vertical wall (side wall 15b) perpendicular to the top surface 14a of the epitaxial layer 14.

Next (FIG. 4), a conductive layer 16, having a thickness smaller than 50 nm, is deposited in a conformable manner, both on the insulation region 15 and on the epitaxial layer 14. The material of the conductive layer 16 is selected on the basis of parameters of resistivity, hardness, stability in temperature, compatibility with CMOS processes and good interface with the storage medium. For example, said material can be a metallic material, such as TiN or a compound thereof (TiN+x=TiNx).

The conductive layer 16 coats in a substantially conformable manner the top wall 15a and the side walls 15b of the insulation region 15, respectively with a top portion 16a and with side portions 16b. As will be explained clearly hereinafter, a side portion 16b of the conductive layer 16 will provide a conductive region of a head of the interaction structure. In particular, the thickness of said layer will determine the pitch of the bits stored within the storage medium or, in a similar way, a smaller dimension W₁ (shown in FIG. 8) of the interaction head (in a first direction x of FIG. 4). In order to provide the conductive layer 16 an appropriate known technique of deposition, for example, a technique of chemical vapor deposition (CVD), is used, enabling a good step coverage and a good thickness control to be achieved.

Next (FIG. 5), a second insulating layer 17, which is also made, for example, of silicon oxide or silicon nitride, is deposited above the conductive layer 16.

A step of planarization of the second insulating layer 17 and of the conductive layer 16 is then carried out (FIG. 6), for example with a technique of chemical-mechanical polishing (CMP). In particular, said planarization step brings about exposure of the insulation region 15 (and possibly a reduction in the height of said insulation region 15), and in addition exposure of the side portions 16b of the conductive layer 16.

Next (FIG. 7), a first etching mask 19 is formed, and a partially isotropic wet etch is performed of the insulation portion 15 and of portions of the second insulating layer 17 that remain after the preceding planarization step. After the etching step, a first insulating portion 20a (which remains after etching of the insulation region 15) and a second insulating portion 20b (which remains after etching of the insulating layer 17) are formed, arranged on opposite sides of a first side portion 16b of the conductive layer 16. The dimensions of the first etching mask 19 are, for example, in the order of some hundreds of nanometers (for example, 200 nm×200 nm), and enable definition, together with the wet-etch parameters, of the dimensions of the insulating portions 20a, 20b in the first direction x and in a second direction y orthogonal to the first direction x. For example, the dimension in the second direction y of the insulating portions 20a, 20b is obtained by subtracting from a corresponding dimension of the first etching mask 19 (in this case 200 nm) an isotropic component of the etch, and typically will be of the order of tens of nanometers, for example, 80 nm.

A second etching mask 21 is then formed (FIG. 8), and a (partially isotropic) wet etch is performed of portions of the conductive layer 16 remaining after the preceding planarization step. The second etching mask 21 has typical minimum dimensions of the order of some hundreds of nanometers (for example, 200 nm) and covers the insulating portions 20a and 20b, part of the aforesaid first side portion 16b of the conductive layer 16, and a portion of the conductive layer connected thereto, whereas it leaves the remaining part of the conductive layer 16 exposed.

As is also shown in FIG. 9, after said etch a first conductive region 22 is defined, arranged between the first insulating portion 20a and the second insulating portion 20b, as well as a first conductive path 23 connected to the first conductive region 22 and set on the epitaxial layer 14; the second insulating portion 20b is arranged on the conductive path 23. In particular, the conductive region 22, together with the first and second insulating portions 20a, 20b form a first interaction head 7 of the interaction structure 6. In a per-se known manner, the first conductive region 22 enables electrical interaction with a corresponding storage medium 4 (for example, made of ferroelectric material), the conductive path 23 enables signals exchanged between the head and the storage medium 4 to be conveyed, and the first and second insulating portions 20a, 20b have the function of insulating the first conductive region 22 and of increasing its mechanical strength. The first conductive region 22 has a substantially rectangular cross section (in a plane parallel to the top surface 14a of the epitaxial layer 14) with a smaller dimension W₁, in the first direction x, of, for example, 20 nm, directly defined by the thickness of deposition of the conductive layer 16 (hence obtained by a non-lithographic process), and a larger dimension W₂, in the second direction y, of, for example, 80 nm, determined by a corresponding dimension of the second etching mask 21 and by an isotropic component of the corresponding etch. The first insulating portion 20a also protects the conductive region 22 from the aforesaid wet etch and contributes to defining its larger dimension W₂.

There follows a step (of a known type and for this reason not described in detail) of definition of the supporting element as a cantilever 5 of the transducer 2 for interaction with the storage medium 4 (as shown in FIG. 10, at an enlarged scale).

In particular, the supporting element 5 is released from the epitaxial layer 14 via MEMS processes of a standard type. The first interaction head 7 is defined on the supporting element 5 at a free end 5a thereof, and the first conductive path 23 extends along a portion of the supporting element 5.

A second embodiment of the present invention envisages exploitation of the process steps previously described for formation of a second interaction head 8, simultaneously to the formation of the first interaction head 7. In particular, in the case where the storage medium 4 comprises ferroelectric material, the first interaction head 7 can be a read head, whilst the second interaction head 8 can be a write head, which enables re-writing of data previously erased during the reading step.

The second embodiment differs from the first embodiment described in the shape of the first and second etching masks 19, 21.

In detail (FIG. 11), the first etching mask 19 comprises in this case a first area 19a, for definition of the insulating portions 20a, 20b belonging to the first interaction head 7, and a second area 19b, for definition of a third insulating portion 20c and a fourth insulating portion 20d which are to form, in a way similar to what has been described previously, the second interaction head 8.

The second etching mask 21 (FIG. 12) has in this case a respective first area 21a for definition of the first conductive region 22 and the first conductive path 23, and a respective second area 21b for definition of a second conductive region 32 and a second conductive path 33 (see also FIG. 13), which is separate and electrically insulated from the first conductive path 23.

FIG. 13 shows the interaction structure 6 thus formed on the epitaxial layer 14, prior to the release of the supporting element. It should in particular be noted that the alignment between the first interaction head 7 and the second interaction head 8 (and, in particular, between the first conductive region 22 and the second conductive region 32) of the interaction structure 6 is automatically guaranteed in the second direction y by the process described.

The advantages of the process are clear from the foregoing description.

In any case, it is underlined that the described process provides, in a simple and inexpensive way, one or more interaction heads 7, 8 having a smaller dimension W₁ that is sub-lithographic. In particular, definition of the smaller dimension W₁ of the conductive regions 22, 32 of the interaction heads (critical dimension of the process) is obtained and controlled with precision via non-lithographic standard processes of deposition of a conformable conductive layer, the thickness of the deposited layer coinciding with said smaller dimension. The advantage that this feature enables is evident:

the process is rendered independent of the costs and technological limits linked to the purely photolithographic processes (which up to now cannot achieve such small dimensions). In addition, as described, also a larger dimension W₂ of said conductive regions is defined without resorting to costly lithographic masks having sub-micrometric dimensions.

The process described further provides an interaction structure 6 having a number of heads integrated on one and the same supporting element 5, made of silicon. Thanks to said process, a self-alignment between said heads can also be guaranteed.

Said solution is particularly advantageous for implementing a process of re-writing of the data in the same position of the ferroelectric storage medium from which they have been read (and erased).

The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheetare incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

In particular, the described dimensions are to be understood as purely indicative and can consequently undergo variations; for example, the smaller dimension W₁ of the interaction head could be other than 20 nm, for example, between 1 and 50 nm, and the larger dimension W₂ could be between 50 and 100 nm.

The interaction structure 6 can be associated to storage media made of non-ferroelectric material or used in any application in which a sub-lithographic smaller interaction dimension is required.

In addition, once the smaller dimension W₁ of the interaction head has been defined via conformable deposition, the subsequent etches that lead to the definition of the head itself can also differ from the one illustrated. For example, the order of the etchings of the insulating and conductive layers could be reversed.

With the described process, a number of interaction heads higher than two can clearly be made by modifying appropriately the etching masks. In addition, the heads thus made may even not be aligned to one another, but arranged according to any desired configuration.

Finally, thanks to the fact that the manufacturing of the interaction structure envisages a cold process, the interaction structure can advantageously be formed also on finished CMOS structures, in the so-called post-processing stage (consequently, not only on an epitaxial layer of a SOI wafer, as illustrated in the figures). In this case, the top surface 14a will be the top surface of a CMOS structure (or wafer).

Claims

1. A transducer for interacting with a storage medium, comprising:

a first interaction head configured to exchange signals with the storage medium, the first interaction head including: a planar first conductive region having a sub-lithographic first dimension in a first direction, and larger second and third dimensions in second and third directions, respectively, that are mutually orthogonal to the first direction; and first and second insulating portions positioned on opposite sides of the first conductive region, the opposite sides being separated from each other by the first dimension of the first conductive region.

2. The transducer according to claim 1, wherein said sub-lithographic first dimension is between 1 and 50 nm.

3. The transducer according to claim 1, further comprising:

a support element having a surface on which the first interaction head is supported; and

a first conductive path electrically coupled to the first conductive region and extending longitudinally on the surface of the support element.

4. The transducer according to claim 3, wherein the first conductive path and the first conductive region are contiguous parts of a unitary conductive layer and the first conductive path extends between the first insulating portion and the surface of the support element.

5. The transducer according to claim 1, wherein the first conductive region has a rectangular shape in a plane that extends in the second and third directions.

6. The transducer according to claim 1, further comprising:

a support element having a surface on which the first interaction head is supported; and

a second interaction head supported on the surface of the support element, the second interaction head having a planar second conductive region having a sub-lithographic dimension, and third and fourth insulating portions positioned on opposite sides of the second conductive region, the opposite sides of the second conductive region being separated from each other by the sub-lithographic dimension of the second conductive region.

7. The transducer according to claim 6, wherein said first and second interaction heads are aligned in the second direction.

8. The transducer according to claim 6, further comprising:

a first conductive path electrically coupled to the first conductive region and extending longitudinally on the surface of the support element; and

a second conductive path electrically coupled to the second conductive region and extending longitudinally on the surface of the support element.

9. The transducer according to claim 8, wherein the second conductive path and the second conductive region are contiguous parts of a unitary conductive layer and the second conductive path extends between the third insulating portion and the surface of the support element.

10. A storage device, comprising:

a storage medium; and

a transducer positioned above the storage medium, the transducer including: a first interaction head configured to exchange signals with the storage medium, the first interaction head including: a planar first conductive region having a sub-lithographic first dimension in a first direction, and larger second and third dimensions in second and third directions, respectively, that are mutually orthogonal to the first direction; and first and second insulating portions positioned on opposite sides of the first conductive region, the opposite sides being separated from each other by the first dimension of the first conductive region.

11. The storage device according to claim 10, wherein said sub-lithographic first dimension is between 1 and 50 nm.

12. The storage device according to claim 10, wherein the transducer includes:

a support element having a surface on which the first interaction head is supported; and

a first conductive path electrically coupled to the first conductive region and extending longitudinally on the surface of the support element.

13. The storage device according to claim 12, wherein the first conductive path and the first conductive region are contiguous parts of a unitary conductive layer and the first conductive path extends between the first insulating portion and the surface of the support element.

14. The storage device according to claim 10, wherein the first conductive region has a rectangular shape in a plane that extends in the second and third directions.

15. The storage device according to claim 10, wherein the transducer includes:

a support element having a surface on which the first interaction head is supported; and

a second interaction head supported on the surface of the support element, the second interaction head having a planar second conductive region having a sub-lithographic dimension, and third and fourth insulating portions positioned on opposite sides of the second conductive region, the opposite sides of the second conductive region being separated from each other by the sub-lithographic dimension of the second conductive region.

16. The storage device according to claim 10, wherein said first and second interaction heads are aligned in the second direction.

17. The storage device according to claim 15, wherein the transducer includes:

a first conductive path electrically coupled to the first conductive region and extending longitudinally on the surface of the support element; and

a second conductive path electrically coupled to the second conductive region and extending longitudinally on the surface of the support element.

18. The storage device according to claim 10, wherein the second conductive path and the second conductive region are contiguous parts of a unitary conductive layer and the second conductive path extends between the third insulating portion and the surface of the support element.

19. A transducer for interacting with a storage medium, comprising:

a support element having a surface;

a first interaction head positioned on the surface of the support element and configured to exchange signals with the storage medium, the first interaction head including: a planar first conductive region having a sub-lithographic first dimension in a first direction; and first and second insulating portions positioned on opposite sides of the first conductive region, the opposite sides being separated from each other by the first dimension of the first conductive region; and

a first conductive path electrically coupled to the first conductive region and extending between the surface of the support element and the first insulating portion.

20. The transducer according to claim 19, wherein said sub-lithographic first dimension is between 1 and 50 nm.

21. The transducer according to claim 19, wherein the first conductive path and the first conductive region are contiguous parts of a unitary conductive layer and the first conductive path extends longitudinally on the surface of the support element.

22. The transducer according to claim 19, further comprising:

a second interaction head supported on the surface of the support element, the second interaction head having a planar second conductive region having a sub-lithographic dimension, and third and fourth insulating portions positioned on opposite sides of the second conductive region, the opposite sides of the second conductive region being separated from each other by the sub-lithographic dimension of the second conductive region.

23. The transducer according to claim 22, further comprising:

a second conductive path electrically coupled to the second conductive region, extending between the third insulating portion and the surface of the support element, and being spaced apart from the first conductive path.