Abstract: A system and method for Acoustic Echo Cancellation. The system and method include a subband affine projection filter and a variable step size controller configured to cancel an estimated echo from a near-end signal. The system and method also include a divergence detector adapted to reset the subband affine projection filter in response to determining a divergence is occurring. Additionally, the system and method include a double talk detector adapted to transmit a signal to mask an output signal when double talk is detected.
Type:
Grant
Filed:
October 24, 2008
Date of Patent:
August 28, 2012
Assignee:
STMicroelectronics Asia Pacific Pte., Ltd.
Inventors:
Muralidhar Karthik, George Sapna, Anoop Kumar Krishna
Abstract: A method of reading voltages from an image sensor having an array of pixels, each pixel having at least one photodiode connectable to a storage node, the method having: controlling each pixel in a row of pixels to transfer charge accumulated in the photodiode above a first threshold to the storage node at the start and end of a first integration period and reading a first voltage at the storage node of each pixel in the row at the end of the first integration period; controlling of the pixels in the row to transfer charge accumulated in the photodiode above a second threshold to the storage node at the start and end of a second integration period longer than the first integration period, and reading a second voltage value at the storage node of each pixel in the row at the end of the second integration period; controlling each pixel in a row of pixels to transfer charge accumulated in the photodiode to the storage node at the end of a third integration period longer than the first and second integration perio
Abstract: The common-mode voltage of a switched-capacitor system is controlled by determining a current common-mode voltage of the switched-capacitor system, converting (in a flow-through conduction cell) the difference between the current common-mode voltage and a desired common-mode voltage into a resultant current, and reinjecting this resultant current into the switched-capacitor system via a resistive path.
Type:
Grant
Filed:
June 11, 2010
Date of Patent:
August 28, 2012
Assignee:
STMicroelectronics (Grenoble 2) SAS
Inventors:
Marc Sabut, Hugo Gicquel, Fabien Reaute
Abstract: A method for following hand movements in an image flow, includes receiving an image flow in real time, locating in each image in the received image flow a hand contour delimiting an image zone of the hand, extracting the postural characteristics from the image zone of the hand located in each image, and determining the hand movements in the image flow from the postural characteristics extracted from each image. The extraction of the postural characteristics of the hand in each image includes locating in the image zone of the hand the center of the palm of the hand by searching for a pixel of the image zone of the hand the furthest from the hand contour.
Type:
Grant
Filed:
January 24, 2008
Date of Patent:
August 28, 2012
Assignees:
STMicroelectronics SA, Universite Paul Cezanne Aix-Marseille III
Inventors:
Lionel Martin, Salah Bourennane, Simon Conseil
Abstract: To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.
Type:
Grant
Filed:
October 30, 2009
Date of Patent:
August 28, 2012
Assignee:
STMicroelectronics, Inc.
Inventors:
Xinde Hu, Sivagnanam Parthasarathy, Shayan Srinivasa Garani, Anthony Weathers, Richard Barndt
Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and in particular to a method of addressing zero-delay frequency switching for cognitive dynamic frequency hopping. The method combines regular (periodic) channel maintenance with dynamic frequency hopping over a cluster of vacated channels that are initially setup such that the switching delays for channel setup and channel availability check are eliminated.
Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.
Type:
Grant
Filed:
May 13, 2011
Date of Patent:
August 28, 2012
Assignee:
STMicroelectronics International N.V.
Inventors:
Paras Garg, Saiyid Mohammad Irshad Rizvi
Abstract: A multi-threshold complementary metal-oxide semiconductor technology (MTCMOS technology) master slave flip-flop with a single clock signal includes a master storage element configured to store an input data in response to a clock signal transition and a slave storage element configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition. The master storage element includes low threshold voltage transistors, the slave storage element includes high threshold voltage transistors, and the master and the slave storage elements are provided with a single clock signal.
Abstract: Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a programming voltage having one of at least a first voltage level for breaking-down the first anti-fuse device but not the second anti-fuse device and coupling the first node to the supply voltage; and a second voltage level for breaking-down the second anti-fuse device but not the first anti-fuse device and coupling the first node to the ground voltage.
Type:
Grant
Filed:
October 3, 2007
Date of Patent:
August 28, 2012
Assignees:
STMicroelectronics (Crolles 2) SAS, Freescale Semiconductor, Inc.
Abstract: An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier.
Abstract: A method processes defects in a radio frequency transmission subsystem due to elements therein. The defects may include mismatch between two channels in phase quadrature in the transmission subsystem and a transposition signal leaking from a first frequency transposition stage of the transmission subsystem. The method may include calibration processing including estimating compensation parameters representative of the defects. The estimating may include delivering, into the transmission subsystem upstream of the elements creating the defects, a reference signal having a reference frequency, obtaining, downstream of the first transposition stage, of a resultant reference signal, and obtaining, from the resultant reference signal, of an approximate value for each compensation parameter. The method also may include compensating for the defects by injecting the approximate values into the transmission subsystem.
Type:
Grant
Filed:
July 20, 2009
Date of Patent:
August 28, 2012
Assignees:
STMicroelectronics N.V., STMicroelectronics (Grenoble) SAS
Abstract: A photosite may include, in a semi-conductor substrate, a photodiode pinched in the direction of the depth of the substrate including a charge storage zone, and a charge transfer transistor to transfer the stored charge. The charge storage zone may include a pinching in a first direction passing through the charge transfer transistor defining a constriction zone adjacent to the charge transfer transistor.
Type:
Application
Filed:
February 16, 2012
Publication date:
August 23, 2012
Applicants:
STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
Abstract: A method is for measuring light energy received by a pixel including a transfer transistor, and a photodiode including a charge storage region. The method may include encapsulating the gate of the transfer transistor of the pixel in a semiconductor layer, at least one part of which includes a hydrogenated amorphous semiconductor. The method also may include grounding the charge storage region of the pixel, and determining the drift over time in the magnitude of the drain-source current of the transfer transistor.
Type:
Application
Filed:
February 22, 2012
Publication date:
August 23, 2012
Applicants:
STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
Abstract: A comparator is configured to generate an output voltage representing the comparison between the absolute value of the difference between two input voltages with an adjustable reference voltage. The comparator includes an input differential amplifier, receiving the two input voltages and connected to an active load network controlled by a control voltage, a control circuit that generates the control voltage representing the adjustable reference voltage, and an output stage having a logic circuit configured to produce the output voltage of the comparator as a logic combination of the output voltages of the differential amplifier.
Type:
Application
Filed:
February 16, 2012
Publication date:
August 23, 2012
Applicants:
Dora S.p.A., STMicroelectronics S.r.l.
Inventors:
Alberto Riva, Giorgio Oddone, Domenico Attianese
Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.
Abstract: A common control channel for base station (“BS”)/consumer premise equipment (“CPE”) communication in areas of overlapping coverage by wireless regional area network (“WRAN”) cells operating on different working channels is disclosed. A common control channel is selected from among the various working channels sensed in each of a plurality of overlapping WRAN cells so as to enable BS/CPE and BS/BS communication. Once chosen, each CPE within the overlapping area communicates with the controlling BS via an enhanced coexistence beacon protocol messages. These messages include timing and other synchronization information.
Type:
Grant
Filed:
June 30, 2011
Date of Patent:
August 21, 2012
Assignee:
STMicroelectronics, Inc.
Inventors:
Liwen Chu, Wendong Hu, George A. Vlantis
Abstract: A cache memory system comprises a cache memory and a cache controller that receives a first address to access the cache memory. The cache controller includes a first address transformer receives the first address and to transform it into one first cache address; the first cache address is used for accessing the cache memory to retrieve a first part of a tag address portion. The cache controller includes a hit detector establishes an partial hit condition based on a comparison of the retrieved a first part of the tag address portion and a first predetermined part of the first address, and a second address transformer receives the first address and to transform it into one second cache address. The cache controller uses the one second cache address for accessing the cache memory to retrieve a data word in case the partial hit condition is established.
Abstract: A bi-directional protection circuit employs a single comparator for detecting fault conditions. Diodes are coupled between a detection node and voltage dividers setting references for inverting and non-inverting comparator inputs, each diode forward biased during one of the positive and negative halves of the alternating current input signal cycle and coupling the detection node to a respective one of the inverting and non-inverting comparator inputs, and reverse biased during the other of the positive and negative halves and decoupling the detection node from the other of the inverting and non-inverting comparator inputs. Upon an overcurrent condition during the positive half, a voltage at the inverting comparator input is drawn above the reference voltage at the non-inverting input. Upon an overcurrent condition during the negative half, a voltage at the non-inverting comparator input is drawn below the reference voltage at the inverting input.
Abstract: A method for determining gain of a back-electromotive force amplifier may include setting an electric motor into a tri-state function mode and storing a first quasi steady-state value for back-electromotive force from the difference signal, and forcing a reference current through the electric motor and determining a first value of the gain of the amplifier for equaling a difference signal to the first quasi steady-state value. The method may further include setting the electric motor into a tri-state function mode a second time and storing a second quasi steady-state value for back-electromotive force from the difference signal, and increasing the first value of the gain by an amount proportional to a difference between the second quasi steady-state value and the first quasi steady-state value.
Type:
Grant
Filed:
December 15, 2009
Date of Patent:
August 21, 2012
Assignee:
STMicroelectronics S.R.L.
Inventors:
Davide Betta, Diego Armaroli, Roberto Trabattoni, Marco Ferrari
Abstract: A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node, such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.