Abstract: A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.

Abstract: A WLAN communication system and algorithm that adaptively changes the data transmission rate of a communication channel based on changing channel conditions. The WLAN communication system or algorithm has two modes being a searching mode and a transmission mode. Furthermore, the WLAN communication system or algorithm incorporates an additive increase, multiplicative decrease (AIMD) function into the rate adaptation algorithm.

Abstract: An optical navigation device may include an image sensor with an imaging surface, a laser, and an optical waveguide layer having an exposed user surface and a total internal reflection (TIR) surface on the underside of the exposed user surface. The waveguide layer, the laser, and the image sensor may be together arranged to direct radiation emitted by the laser onto the imaging surface at least partly by total internal reflection by the TIR surface.

Abstract: A method for controlling a contact angle between a glue and a surface of a substrate during manufacture of microchip packages is disclosed. The method includes applying a glue to a surface of a substrate, and placing an electrode in electrical connection with the glue. A potential difference is applied between the electrode and the substrate. The potential difference is applied across the glue and causes a contact angle between the glue and the surface of the substrate to be altered.

Abstract: A semiconductor thermoelectric cooler is configured to direct heat through channels of the cooler. The thermoelectric cooler has multiple electrodes and a first dielectric material positioned between side surfaces of the electrodes. A second dielectric material, different from the first dielectric material, is in contact with top surfaces of the electrodes. The first dielectric material extends above the top surface of the electrodes, separating portions of the second dielectric material, and is in contact with a portion of the top surfaces of the electrodes. The first dielectric material has a thermal conductivity different than a thermal conductivity of the second dielectric material. A ratio of the first dielectric material to the second dielectric material in contact with the top surface of the electrodes may be selected to control the heat retention. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract: A circuit simulator includes at least one clock generator. The at least one clock generator is configured to generate at least one root clock signal for an associated clock domain part of the circuit under simulation. The circuit simulator also includes a clock modifier configured to generate at least one delay to be applied to at least one of the at least one root clock signal.

Abstract: A semiconductor thermoelectric cooler includes P-type and N-type thermoelectric cooling elements. The P-type and N-type thermoelectric elements have a first portion having a first cross-sectional area and a second portion having a second cross-sectional area larger than the first cross-sectional area. The P-type and N-type thermoelectric cooling elements may, for example, be T-shaped or L-shaped. In another example, the thermoelectric cooling elements have a first surface having a first shape configured to couple to a first electrical conductor and a second surface opposite the first surface and having a second shape, different from the first shape, and configured to couple to a second electrical conductor. For example, the first surface may have a rectilinear shape of a first area and the second surface may have a rectilinear shape of a second area different from the first area. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract: The present disclosure relates to a method for measuring a capacitance of a pair of electrodes including charging the pair of electrodes and transferring the charge between the pair of electrodes and a sampling capacitor, and a measuring step representative of the capacitance of the pair of electrodes according to the voltage at the terminals of the sampling capacitor according to the number of cycles executed so that the voltage at the terminals of the sampling capacitor reaches a threshold voltage. According to the present disclosure, the method comprises an initial step of charging the sampling capacitor between a first voltage and a second intermediate voltage in between the first voltage and a third voltage greater than or equal to a ground voltage, the pair of electrodes being charged between the second voltage and the third voltage. The present disclosure applies in particular to the control of a touch pad.

Abstract: Receiving circuitry having a plurality of amplifiers coupled in series, a first of the amplifiers receiving an input signal and each of the amplifiers outputting an amplified signal; a plurality of comparators each coupled to the output of one of the amplifiers and having an input for receiving the amplified signal; signal identification circuitry coupled to the outputs of the comparators and arranged to determine whether the outputs of the comparators validly represent data; and signal selection circuitry arranged to select the best signal originating from the comparators based on the validity of the outputs of the comparators.

Abstract: The disclosure relates to an electronic differential amplification device integrated on a semiconductor chip. The device may include first and second transistors having respective source terminals connected to a first potential, and drain terminals to receive a first differential current signal. The device may include third and fourth transistors having respective source terminals connected to the first potential, and drain terminals to provide a second differential current signal to a load obtained by amplifying the first signal. The third and fourth transistors may have a respective gate terminal connected to the drain terminal of the first and the second transistors, respectively, in order to form current mirrors with the latter.

Abstract: A method and a circuit for checking the coherence between data read from a first area of a memory of a microcontroller and the address of these data, including calculating a current digital signature of the read data by a function also taking into account the address of these data in the memory, and checking the coherence between the current signature and a previously-recorded signature.

Abstract: An image sensor formed in a semiconductor stack of a lower region of a first conductivity type and of an upper region of a second conductivity type, including: a photodiode formed of a first portion of the stack; a read area formed of a second portion of the stack; a trench with insulated walls filled with a conductive material, the trench surrounding the photodiode and the read area and being interrupted, all along its height, on a portion facing the photodiode and the read area; and first connection mechanism associated with the conductive material of the trench and capable of being connected to a reference bias voltage.

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract: A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein.

Abstract: An embodiment of a power-supply controller comprises a switching-control circuit, an error amplifier, and a signal generator. The switching-control circuit is operable to control a switch coupled to a primary winding of a transformer, and the error amplifier has a first input node operable to receive a feedback signal, a second input node operable to receive a comparison signal, and an output node operable to provide a control signal to the switching-control circuit. The signal generator is operable to generate either the feedback signal or the comparison signal in response to a compensation signal that is isolated from a secondary winding of the transformer and that is proportional to a load current through a conductor disposed between the secondary winding and a load.

Abstract: The method includes defining from all the check nodes at least one group of check nodes mutually connected through at least one second variable node defining an internal second variable node. The method includes performing for each group the joint updating of all the check nodes of the group via a Maximum-A-Posteriori (MAP) type process, and the updating of all the first variable nodes and all the second variable nodes connected to the group except the at least one internal second variable node. The method may include iteratively repeating the updates.

Abstract: An integrated-circuit semiconductor device includes external electrical connection pads on one face and electrical connection vias under said pads. The electrical connection vias are arranged with a defined pitch in a defined direction. Each via is respectively associated with one of a plurality of adjacent zones of the face. These zones extend perpendicularly to the pitch direction. The electrical connection pads are grouped in adjacent pairs. An insulation space is located between the pads of each pair of electrical connection pads. In a direction perpendicular to the pitch direction, the pads in the pair are spaced apart. The pads of each pair of electrical connection pads extend over a pair of adjacent zones and are associated with two adjacent vias.

Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.

Abstract: A monitoring device may include a core cell including a detection circuit, and a radio frequency (RF) tag antenna configured to exchange data with a data acquisition reader device, and a single-tier corolla having sensor cells around the core cell and covering a monitoring area. The sensor cells may be configured to convert a change of a parameter at the cell location. The detection circuit may be configured to detect a change in the parameter and location based upon excitation by the reader device.

Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.