Abstract: A control circuit receives a first clock signal at a first frequency, a frequency division signal specifying a divisor number, and a second clock signal at a second frequency (higher than the first frequency). The control circuit includes a phase control block that defines non-overlapping portions of a pulse of the second clock to include center, left and right portions. A determination is then made as to whether an edge of the first clock is located within the center portion. In response to such a determination, a number of periods of the second clock signal which occur within one or more periods of the first clock signal is compared to a number derived from the divisor number to generate a frequency selection signal indicative of that comparison. A controlled oscillator circuit generates the second clock signal at the second frequency, wherein the second frequency is specified by the frequency selection signal.

Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.

Abstract: A micro-electro-mechanical system (MEMS) actuator circuit and method. The circuit includes a current mirror, a voltage divider having an interior contact and coupled between the mirror output and a potential, an operational amplifier having an input coupled to the interior contact and a switch having input/output contacts separately coupled to the amplifier output and the mirror input and having a switch control. The amplifier output can be coupled to a digital control circuit which can be coupled to the switch control contact and to a digital to analog circuit (DAC) which can be coupled to the digital control circuit and to another amplifier input. An enable signal at the switch control couples the switch input/output contacts together. The capacitance of a MEMS capacitor coupled to the mirror output is determined by measurement of time for the amplifier output to switch from one level to another following a change in DAC output potential.

Abstract: A communication system includes interfacing between a first synchronous circuit and a second synchronous circuit. The system includes a first interface system and a second interface system. The first interface system receives data from the first synchronous circuit, and encodes the data according to an asynchronous communication protocol. The encoded data are transmitted over a communication channel to the second interface system. The second interface system decodes the data and transmits the decoded data to the second synchronous circuit. The first interface system includes a first FIFO memory for storing temporarily the data received from the first synchronous circuit and the second interface system includes a second FIFO memory for storing temporarily the data transmitted over the communication channel.

Abstract: An embodiment in a single structure combines a pad comprising a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside the chip itself and at least one inductor that can be used to receive/transmit electromagnetic waves or to supply the chip with power or both. By combining a connection pad and an inductor in a single structure, it is possible to reduce the overall area that otherwise would be occupied exclusively by the inductors, thus reducing the cost and size of integrated circuits that include such a structure.

Abstract: According to one implementation, the slave identifier bits are tested recursively in groups of p bits. For these p bits, each slave will recognize, in its p corresponding identifier bits, one combination out of the 2p possible combinations. The slaves respond simultaneously (20) over the bus, for example an I2C bus, to a request from the master. The response is given by outputting a series of “1” bits in which each slave inserts a “0”, which is, for example, the priority logic value on the bus, the position of the “0” in the series of “1” bits being dependent on the binary value of the combination recognized by the slave in the group of p bits of its identifier. The master progressively determines on the fly, based on the bits of the frame received, the values of bits of these digital information items.

Abstract: When two loudspeakers play the same signal, a “phantom center” image is produced between the speakers. However, this image differs from one produced by a real center speaker. In particular, acoustical crosstalk produces a comb-filtering effect, with cancellations that may be in the frequency range needed for the intelligibility of speech. Methods for using phase decorrelation to fill in these gaps and produce a flatter magnitude response are described, reducing coloration and potentially enhancing dialogue clarity. These methods also improve headphone compatibility and reduce the tendency of the phantom image to move toward the nearest speaker.

Abstract: Described herein is a biasing circuit for a magnetic-field sensor; the magnetic-field sensor is provided with a first detection structure, which generates a first electrical detection quantity as a function of a first component of an external magnetic field, and a second detection structure, which generates a second electrical detection quantity as a function of a second component of an external magnetic field. The biasing circuit electrically supplies the first detection structure and the second detection structure in respective biasing time intervals, at least partially distinct from one another, which preferably do not temporally overlap one other.

Abstract: A device for generating electrical energy from the heat dissipated by a heat source, comprising: a capacitor comprising two electrodes between which a ferroelectric material is present, said capacitor being arranged so as to be positioned to capture all or part of the heat dissipated by said heat source; a capacitive element a first electrode of which is connected to a first electrode of said capacitor; a recovery circuit interposed between the second electrode of said capacitor and the second electrode of the capacitive element, and able to have the current flowing between said second electrodes pass through it. a mechanism adapted to move the capacitor with respect to the heat source, said mechanism having at least one arm able to move between two positions, the capacitor being closer to the heat source in one of the two positions.

Abstract: The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part of a standard integrated circuit process. The localized and passive removal of thermal energy achieved at the circuit level rather just at the package level is both more effective and more efficient.

Abstract: Three alternative methods of controlling transmit power in a basic service set (BSS) including a plurality of stations that have successfully synchronized with an access point include providing each BSS with one transmit power limit that is not more than the lowest one of the transmit power limits of all of its operating channels, providing each BSS with one transmit power limit that is fixed for physical layer convergence procedure (PLCP) protocol data units (PPDU) with each channel bandwidth, or providing each BSS with one transmit power limit that is fixed for each 80 MHz channel.

Abstract: A semiconductor device includes an assembly of two integrated circuits. The assembly has a layer of photoresist filling the space between the two integrated circuits, and at least one electrically conducting pillar within the resist and electrically coupling the two integrated circuits.

Abstract: Switch including a terminal of a first type and at least two terminals of a second type, and a number of circuits capable of ensuring exclusive connection of one of the terminals of the second type to the terminal of the first type as a function of a set of control orders wherein the terminal of the first type is connected to a common point by a first circuit; each terminal of the second type is connected to the common point by a second circuit, with each second circuit including a portion that is magnetically coupled to the first circuit, a static switch mounted in parallel with the portion and capable of being controlled in the “off” state in order to connect the terminal of the first type to the terminal of the second type associated with the second circuit in question.

Abstract: An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information.

Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

Abstract: A method of fabricating an image sensor includes the steps of: forming at least two photosites in a semiconductor substrate; forming a trench between the photosites; forming a thin liner on at least the sidewalls of the trench; depositing a conductive material having a first refractive index in the trench; and forming a region surrounded by the conductive material and having a second refractive index lower than the first index of refraction within the conductive material in the trench.

Abstract: A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.

Abstract: An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.

Abstract: An image sensor having a semiconductor substrate, at least two photosites in the substrate and an isolation region between the photosites. The isolation region has a first trench covered by a thin electrically insulating liner and filled with an electrically conductive material, the conductive material has a second trench at least partially filled with an optically isolating material.

Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.