Abstract: In one embodiment, an electro-optical modulator includes a waveguide having a first major surface and a second major surface opposite the first major surface. A cavity is disposed in the waveguide. Multiple quantum wells are disposed in the cavity.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

Abstract: A MEMS switch is actuatable by a fluid, and includes a piezoelectric pressure sensor that detects the movement of a fluid generating a negative pressure. The piezoelectric pressure sensor is formed by a chip of semiconductor material having a through cavity and a sensitive membrane, which extends over the through cavity and has a first and a second surface. The piezoelectric pressure sensor is mounted on a face of a board having a through hole so that the through cavity overlies and is in fluid connection with the through hole. The board has a fixing structure, which enables securing in an opening of a partition wall separating a first and a second space from each other. The board is arranged so that the first surface of the sensitive membrane faces the first space, and the second surface of the sensitive membrane faces the second space.

Abstract: An oscillator includes a tunable resonant circuit having an inductance and a variable capacitance coupled between first and second nodes, and a set of capacitances selectively coupleable between the first and second nodes. An input control node receiving an input control signal is coupled to the variable capacitance and set of capacitances. The tunable resonant circuit is tunable based on the input control signal. A biasing circuit biases the tunable resonant circuit to generate a variable-frequency output signal between the first and second nodes. A voltage divider generates a set of different voltage thresholds, and a set of comparator circuits with hysteresis compares the input control signal to the set of different voltage thresholds to generate a set of control signals. The capacitances in the set of capacitances are selectively coupleable between the first and second nodes as a function of control signals in the set of control signals.

Abstract: An image sensor includes an array of pixels inside and on top of a substrate. A control circuit is configured to apply voltage potentials to the substrate. During a first phase, the control circuit applies a ground potential to the substrate. During a second phase, the control circuit applies a potential positive with respect to the ground potential to the substrate.

Abstract: A MEMS actuator includes a semiconductor body with a first surface defining a housing cavity facing the first surface and having a bottom surface, the semiconductor body further defining a fluidic channel in the semiconductor body with a first end across the bottom surface. A strainable structure extends into the housing cavity, is coupled to the semiconductor body at the bottom surface, and defines an internal space facing the first end of the fluidic channel and includes at least a first and a second internal subspace connected to each other and to the fluidic channel. When a fluid is pumped through the fluidic channel into the internal space, the first and second internal subspaces expand, thereby straining the strainable structure along the first axis and generating an actuation force exerted by the strainable structure along the first axis, in an opposite direction with respect to the housing cavity.

Abstract: A converter includes first and second transistors coupled between first and second nodes, and first and second thyristors coupled between the first and second nodes. The converter is controlled for operation to: in first periods, turn the first transistor and second thyristor on and turn the second transistor and the first thyristor off, and in second periods, turn the first transistor and the second thyristor off and turn the second transistor and the first thyristor on. Further control of converter operation includes, for a third period following each first period, turning the first and second transistors off, turning the second thyristor off, and injecting a current into the gate of the first thyristor. Additional control of converter operation includes, for a fourth period following each second period, turning the first and second transistors off, turning the first thyristor off, and injecting a current into the gate of the second thyristor.

Abstract: A sensing pixel includes a single photon avalanche diode (SPAD) coupled between a first node and a second node, with a clamp diode being coupled between a turn-off voltage node and the second node. A turn-off circuit includes a sense circuit configured to generate a feedback voltage based upon a voltage at the turn-off voltage node, a transistor having a first conduction terminal coupled to the turn-off voltage node, a second conduction terminal coupled to ground, and a control terminal, and an amplifier having a first input coupled to a reference voltage, a second input coupled to receive the feedback voltage, and an output coupled to the control terminal of the transistor. A readout circuit is coupled to the SPAD by a decoupling capacitor.

Abstract: A control system includes a mirror controller generating horizontal and vertical mirror synchronization signals for a mirror based upon a mirror clock signal. Laser modulation circuitry generates horizontal and vertical laser synchronization signals as a function of first and second laser clock signals and generates control signals for a laser that emits a laser beam that impinges on the mirror. First synchronization circuitry receives the horizontal mirror synchronization signal and the horizontal laser synchronization signal, and modifies generation of the first laser clock signal to achieve alignment between the horizontal mirror synchronization signal and horizontal laser synchronization signal. Second synchronization circuitry receives the vertical mirror synchronization signal and the vertical laser synchronization signal, and modifies generation of the second laser clock signal to achieve alignment between the vertical mirror synchronization signal and vertical laser synchronization signal.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

Abstract: A package for integrated circuits includes a base substrate having a mounting face. A first electronic chip has a top face electrically connected to the mounting face and a bottom face mounted to the mounting face by an adhesive layer. A second electronic chip has a bottom face covered with a thermal interface layer and a top face electrically connected to the mounting face. A heat sink includes a first part embedded in the adhesive layer, a second part having a bottom face in contact with the layer of thermal interface material and a top face, and a connection part between the first part and the second part. A coating encapsulates the first and second electronic chips and the heat sink. The top face of the second part of the heat sink exposed from the encapsulating coating.

Abstract: In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

Abstract: An embodiment apparatus comprises an optically transparent substrate having first and second surfaces; a piezoelectric membrane, arranged at the first surface, that oscillates in response to a light beam propagated through the substrate; at least one reflective facet facing the substrate and arranged at the piezoelectric membrane; and an optical element receiving the light beam at an input end and guiding the light beam towards an output end coupled to the second surface. The optical element incorporates a light focusing path focusing the light beam at a focal point at the piezoelectric membrane, and at least one light collimating path collimating the light beam onto the at least one reflective facet. The optical element guides light reflected from the at least one reflective facet to the input end, the reflected light indicating a position of the optical element with respect to the focal point.

Abstract: A convolutional neural network includes convolution circuitry. The convolution circuitry performs convolution operations on input tensor values. The convolutional neural network includes requantization circuitry that requantizes convolution values output from the convolution circuitry.

Abstract: A power switch device includes a first terminal intended to be connected to a source of a first supply potential, a second terminal configured to supply a second potential, and a third terminal intended to be connected to a second source of a third supply potential. The device includes a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal, a second PMOS transistor having a source connected to the second terminal, and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second transistor. A control circuit generates gate control signals to control operation of the first, second and third PMOS transistors dependent on the first, second, and third supply potentials.

Abstract: An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.

Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.

Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

Abstract: A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.