Patents Assigned to STMicroelectronics
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Patent number: 11575172Abstract: An electronic device includes a base substrate with a mica substrate thereon. A top face of the mica substrate has a surface area smaller than a surface area of a top face of the base substrate. An active battery layer is on the mica substrate and has a top face with a surface area smaller than a surface area of a top face of the mica substrate. An adhesive layer is over the active battery layer, mica substrate, and base substrate. An aluminum film layer is over the adhesive layer, and an insulating polyethylene terephthalate (PET) layer is over the aluminum film layer. A battery pad is on the mica substrate adjacent the active battery layer, and a conductive via extends to the battery pad. A conductive pad is connected to the conductive via. The adhesive, aluminum film, and PET have a hole defined therein exposing the conductive pad.Type: GrantFiled: January 5, 2022Date of Patent: February 7, 2023Assignee: STMicroelectronics (Tours) SASInventor: Vincent Jarry
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Publication number: 20230035445Abstract: An encapsulation of laser direct structuring (LDS) material is molded onto first and second semiconductor dice. A die-to-die coupling formation between the first and second semiconductor dice includes die vias extending through the LDS material to reach the first and second semiconductor dice and a die-to-die line extending at a surface of the encapsulation between the die vias. After laser activating and structuring selected locations of the surface of the encapsulation for the die vias and die-to-die line, the locations are placed into contact with an electrode that provides an electrically conductive path. Metal material is electrolytically grown onto the locations of the encapsulation by exposure to an electrolyte carrying metal cations. The metal cations are reduced to metal material via a current flowing through the electrically conductive path provided via the electrode. The electrode is then disengaged from contact with the locations having metal material electrolytically grown thereon.Type: ApplicationFiled: July 25, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Dario VITELLO, Michele DERAI
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Publication number: 20230031682Abstract: A pre-molded substrate for semiconductor devices includes a sculptured electrically conductive (e.g., copper) laminar structure having spaces therein. The laminar structure includes one or more die pads having a first die pad surface configured to have semiconductor chips mounted thereon. A pre-mold material molded onto the laminar structure penetrates into the spaces therein and provides a laminar pre-molded substrate including the first die pad surface left exposed by the pre-mold material with the die pad(s) bordering on the pre-mold material. One or more stress-relief curved portions are provided at the periphery of one or more of the die pads. The stress-relief curved portions are configured to border on the pre-mold material over a smooth surface to effectively counter the formation of cracks in the pre-mold material as a result of the pre-molded substrate being bent.Type: ApplicationFiled: July 21, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventor: Mauro MAZZOLA
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Publication number: 20230030472Abstract: An optical sensor includes pixels, with each pixel formed by a photodetector and a telecentric system topping the photodetector. Each telecentric system includes: an opaque layer with openings facing the photodetector and a microlens facing each opening and arranged between the opaque layer and the photodetector. Each pixel further includes an optical filter between the microlenses and the photodetector. The optical filter may, for example, be an interference filter, a diffraction grating-based filter or a metasurface-based filter.Type: ApplicationFiled: July 20, 2022Publication date: February 2, 2023Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SASInventors: Axel CROCHERIE, Olivier LE-BRIZ
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Publication number: 20230033569Abstract: A finite impulse response (FIR) filter includes a plurality of registers. The data input terminal of each register is directly coupled to the input of the FIR filter. A new data value is passed to each register on each clock cycle of a filter clock signal. Only one of the registers processes the data value on each clock cycle. A ring counter is coupled to the registers and determines which register processes the data value on each dock cycle.Type: ApplicationFiled: July 18, 2022Publication date: February 2, 2023Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Rupesh SINGH
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Publication number: 20230034445Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.Type: ApplicationFiled: October 13, 2022Publication date: February 2, 2023Applicant: STMicroelectronics (Grenoble 2) SASInventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
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Publication number: 20230029946Abstract: The present description concerns an electromagnetic wave transmit/receive device comprising a multilayer organic substrate, an integrated circuit chip, flip-chip assembled on the multilayer organic substrate, a package comprising a first cavity, containing the multilayer organic substrate and the integrated circuit chip, and communicating over a channel with a second cavity forming a waveguide for electromagnetic waves.Type: ApplicationFiled: July 22, 2022Publication date: February 2, 2023Applicants: STMicroelectronics SA, STMicroelectronics (Grenoble 2) SASInventors: Victor FIORESE, Jean-Francois CAILLET, Frederic GIANESELLO, Fanny LAPORTE
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Publication number: 20230034786Abstract: First and second circuit branches are coupled between an input node and ground. Each circuit branch includes a series coupling first-fourth transistors in a current flow path with an output node. A first capacitor is coupled between a first capacitor node and a second capacitor node intermediate the first transistor and the second transistor in the first circuit branch. A second capacitor is coupled between a third capacitor node and a fourth capacitor node intermediate the first transistor and the second transistor in the second circuit branch. An inter-branch circuit block between the first and second branches includes a first inter-branch transistor coupled between the first capacitor node in the first circuit branch and the fourth capacitor node in the second circuit branch and a second inter-branch transistor coupled between the third capacitor node in the second circuit branch and the second capacitor node in the first circuit branch.Type: ApplicationFiled: July 20, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Alessandro DAGO, Alessandro GASPARINI, Osvaldo Enrico ZAMBETTI, Salvatore LEVANTINO, Massimo Antonio GHIONI
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Publication number: 20230032635Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.Type: ApplicationFiled: August 2, 2021Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Simone Dario MARIANI, Elisabetta PIZZI, Daria DORIA
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Publication number: 20230032898Abstract: A memory cell includes a substrate with a semiconductor region and an insulating region. A first insulating layer extends over the substrate. A phase change material layer rests on the first insulating layer. The memory cell further includes an interconnection network with a conductive track. A first end of a first conductive via extending through the first insulating layer is in contact with the phase change material layer and a second end of the first conductive via is in contact with the semiconductor region. A first end of a second conductive via extending through the first insulating layer is in contact with both the phase change material layer and the conductive track, and a second end of the second conductive via is in contact only with the insulating region.Type: ApplicationFiled: July 27, 2022Publication date: February 2, 2023Applicants: STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SASInventors: Paolo Giuseppe CAPPELLETTI, Fausto PIAZZA, Andrea REDAELLI
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Publication number: 20230036484Abstract: A testing device for electronic dies includes a first support part and a second support part configured to be removably assembled with each other. The first and second support parts together define at least one housing where at least one electronic die can be arranged to be tested. The electronic die has a first surface with contacting elements. The at least one housing includes a first portion. This at least one housing is arranged to enable the at least one electronic die to occupy a first position in the housing where the first surface is spaced apart from the first portion, and is further arrange to enable the at least one electronic die to occupy a second position in the housing where the first surface bears against the first portion.Type: ApplicationFiled: July 20, 2022Publication date: February 2, 2023Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: Klodjan BIDAJ, Benjamin ARDAILLON, Lauriane GATEKA
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Publication number: 20230035607Abstract: A microelectromechanical (MEMS) structure includes a fixed frame internally defining a cavity, and a mobile mass suspended in the cavity and movable with a first resonant rotational mode about a first rotation axis and with a second resonant rotational mode about a second rotation axis orthogonal to the first. A pair of supporting elements extends in the cavity, is rigidly coupled to the fixed frame, and is elastically deformable to cause rotation of the mobile mass about the first rotation axis. A pair of elastic-coupling elements is elastically coupled between the mobile mass and the first pair of supporting elements. Each of the elastic-coupling elements includes a first and second elastic portions, the first elastic portion being compliant to torsion about the second rotation axis. The second elastic portion is compliant to bending outside of a horizontal plane of main extension of the MEMS structure.Type: ApplicationFiled: October 12, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Nicolo' BONI, Roberto CARMINATI, Massimiliano MERLI
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Publication number: 20230031356Abstract: A pre-molded leadframe includes a laminar structure having empty spaces therein and a first thickness with a die pad having opposed first and second die pad surfaces. Insulating pre-mold material is molded onto the laminar structure. The pre-mold material penetrates the empty spaces and provides a laminar pre-molded substrate having the first thickness with the first die pad surface left exposed. The die pad has a second thickness that is less than the first thickness. One or more pillar formations are provided protruding from the second die pad surface to a height equal to a difference between the first and second thicknesses. With the laminar structure clamped between surfaces of a mold, the first die pad surface and pillar formations abut against the mold surfaces. The die pad is thus effectively clamped between the clamping surfaces countering undesired flashing of the pre-mold material over the first die pad surface.Type: ApplicationFiled: July 26, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Mauro MAZZOLA, Roberto TIZIANI
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Publication number: 20230032786Abstract: A leadframe includes a die pad having arranged thereon a first semiconductor die with an electrically conductive ribbon extending on the first semiconductor die. The first semiconductor die lies intermediate the leadframe and the electrically conductive ribbon. A second semiconductor die is mounted on the electrically conductive ribbon to provide, on the same die pad, a stacked arrangement of the second semiconductor die and the first semiconductor die with the at least one electrically conductive ribbon intermediate the first semiconductor die and the second semiconductor die. Package size reduction can thus be achieved without appreciably affecting the assembly flow of the device.Type: ApplicationFiled: July 26, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Matteo DE SANTA, Mirko ALESI
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Publication number: 20230031422Abstract: A pre-molded substrate includes a sculptured, electrically conductive laminar structure having spaces therein. The laminar structure includes a die pad having a first die pad surface configured to mount a semiconductor chip. A pre-mold material molded onto the laminar structure penetrates into the spaces and provides a laminar pre-molded substrate with the first die pad surface left exposed. The peripheral edge of the die pad includes an alternation of first and second anchoring formations to the pre-mold material. The first anchoring formations counter first detachment forces inducing displacement of the die pad with respect to the pre-mold material in a first direction from the second die pad surface to the first die pad surface. The second anchoring formations counter second detachment forces inducing displacement of the die pad with respect to the pre-mold material in a second direction from the first die pad surface to the second die pad surface.Type: ApplicationFiled: July 22, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventor: Mauro MAZZOLA
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Publication number: 20230035470Abstract: An encapsulation of laser direct structuring (LDS) material is molded onto a substrate having first and second semiconductor dice arranged thereon. Laser beam energy is applied to a surface of the encapsulation of LDS material to structure therein die vias extending through the LDS material to the first and second semiconductor dice and a die-to-die line extending at surface of the LDS material between die vias. Laser-induced forward transfer (LIFT) processing is applied to transfer electrically conductive material to the die vias and the die-to-die line extending between die vias. A layer of electrically conductive material electroless grown onto the die vias and the die-to-die line facilitates improved adhesion of the electrically conductive material transferred via LIFT processing.Type: ApplicationFiled: July 25, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Andrea ALBERTINETTI, Mirko ALESI
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Publication number: 20230032887Abstract: Described herein is a method of forming wafer-level packages from a wafer. The method includes adhesively attaching front sides of first integrated circuits within the wafer to back sides of second integrated circuits such that pads on the front sides of the first integrated circuits and pads on front sides of the second integrated circuits are exposed. The method further includes forming a laser direct structuring (LDS) activatable layer over the front sides of the first integrated circuits and the second integrated circuits and over edges of the second integrated circuits, and forming desired patterns of structured areas within the LDS activatable layer. The method additionally includes metallizing the desired patterns of structured areas to form conductive areas within the LDS activatable layer.Type: ApplicationFiled: July 8, 2022Publication date: February 2, 2023Applicant: STMicroelectronics Pte LtdInventor: Jing-En LUAN
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Patent number: 11567471Abstract: A resolver decoder circuit includes: a first filter circuit configured to calculate a first weighted sum of a first digital signal over a pre-determined period of time, where the first digital signal includes first digital samples of a first analog signal from a sine winding of a resolver; a second filter circuit configured to calculate a second weighted sum of a second digital signal over the pre-determined period of time, where the second digital signal includes second digital samples of a second analog signal from a cosine winding of the resolver, where the first and the second analog signals are configured to be induced by a sine signal applied to an input winding of the resolver; and a rectifier configured to generate a first output and a second output by adjusting a first sign of the first weighted sum and adjusting a second sign of the second weighted sum, respectively.Type: GrantFiled: June 28, 2021Date of Patent: January 31, 2023Assignee: STMicroelectronics (China) Investment Co.Inventors: Jian Wang, Luting Ye, Xiaobo Sun
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Patent number: 11568515Abstract: An embodiment method for converting an initial digital image into a converted digital image, electronic chip, system and computer program product are disclosed, the initial digital image comprising a set of pixels, the pixels being associated respectively with colors, the initial digital image being acquired by an acquisition device, and the converted digital image able to be used by a neural network. The embodiment method comprises redimensioning of the initial digital image in order to obtain an intermediate digital image, the redimensioning being carried out by a reduction in the number of pixels of the initial image, modification of a format of one of the pixels of the intermediate digital image in order to obtain a converted digital image, the modification being carried out, after the redimensioning, by increasing the number of bits used to represent the color of the pixel.Type: GrantFiled: June 29, 2021Date of Patent: January 31, 2023Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SASInventors: Julien Closs, Jean-Michel Delorme, Daniel Fauvarque, Laurent Folliot, Guillaume Legrain
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Patent number: 11569021Abstract: A transformer of the symmetric-asymmetric type includes comprising a primary inductive circuit and a secondary inductive circuit formed in a same plane by respective interleaved and stacked metal tracks. A first crossing region includes a pair of connection plates facing one another, with each connection plate having a rectangular shape that is wider than the metal tracks, and diagonally connected to tracks of the secondary inductive circuit.Type: GrantFiled: February 13, 2019Date of Patent: January 31, 2023Assignee: STMicroelectronics SAInventor: Vincent Knopik