Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits.

Abstract: A system on chip includes a non-volatile memory and a processor configured to execute an operating system which receives data according to a first communication protocol and program installation software that communicates with the non-volatile memory according to a second communication protocol. The operating system functions to: determine whether data received according to the first communication protocol is program data, make the program data available to the installation software, and inform the installation software that program data has been received. The installation software then stores the program data in the non-volatile memory.

Abstract: Described herein is an electric motor drive system, including at least one power phase line, an external controller configured to generate a drive signal and provide the drive signal to the at least one power phase line, and motor electronics. The motor electronics include at least one switch coupled between the at least one power phase line and at least one electric motor terminal, and an internal controller configured to cooperate with the external controller to perform an authentication process therebetween. The external controller is further configured to cause the at least one switch to electrically couple the at least one power phase line to the at least one electric motor terminal in response to success of the authentication process.

Abstract: A closed-loop microelectromechanical accelerometer includes a substrate of semiconductor material, an out-of-plane sensing mass and feedback electrodes. The out-of-plane sensing mass, of semiconductor material, has a first side facing the supporting body and a second side opposite to the first side. The out-of-plane sensing mass is also connected to the supporting body to oscillate around a non-barycentric fulcrum axis parallel to the first side and to the second side and perpendicular to an out-of-plane sensing axis. The feedback electrodes are capacitively coupled to the sensing mass and are configured to apply opposite electrostatic forces to the sensing mass.

Abstract: A control method of an apparatus is provided. The apparatus includes a control unit coupled to a proximity sensor to detect a first distance of a user in a field of view, and coupled to a charge variation sensor to detect an electric/electrostatic charge variation caused by the user in a detection region. The control method includes acquiring a charge variation signal and generating charge variation parameters as a function of the charge variation signal. The control method further includes determining whether a condition on charge variation parameters is verified, and if the condition on charge variation parameters is verified, activating the proximity sensor and acquiring a proximity signal. Proximity parameters are generated as a function of the proximity signal. If a condition on proximity parameters is verified, one or more functionalities of the apparatus are activated.

Abstract: A wireless device includes an energy harvester and an energy storage that operate in a sequence of energy harvesting cycles to alternately harvest energy and release energy for supplying the wireless device. The wireless device also includes a processing circuit and a wireless communication circuit. A configuration method for the wireless device includes first step where a base station receives a signal from the wireless device indicating wireless communication circuit entry into a receiving operation mode. In a second step, the base station transmits configuration data to the wireless device. The received configuration data is temporarily stored in a memory area of the wireless communication circuit. In a third step, the temporarily stored configuration data is transmitted from the wireless communication circuit to the processing circuit for storage in a memory area. The second and third steps are carried out during distinct energy harvesting cycles of the wireless device.

Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.

Abstract: A detection method of a user of an apparatus is provided in which the apparatus is coupled to a charge variation sensor having a control unit and an electrode to detect an electric/electrostatic charge variation of the user. The detection method includes acquiring, through the electrode, a charge variation signal indicative of the presence of the user. A filtered signal is generated by filtering the charge variation signal. A feature signal is generated as a function of the filtered signal. A movement signal indicative of a movement of the user is generated as a function of the feature signal. A presence signal indicative of the presence of the user is generated as a function of the movement signal.

Abstract: A touchscreen resistive sensor includes a network of resistive sensor branches coupled to a number of sensor nodes arranged at touch locations of the touchscreen. A test sequence is performed by sequentially applying to each sensor node a reference voltage level, jointly coupling to a common line the other nodes, sensing a voltage value at the common line, and declaring a short circuit condition as a result of the voltage value sensed at the common line reaching a short circuit threshold. A current value level flowing at the sensor node to which the reference voltage level is applied is sensed and a malfunction of the resistive sensor branch coupled with the sensor node to which a reference voltage level is applied is generated as a result of the current value sensed at the sensor node reaching an upper threshold or lower threshold.

Abstract: A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.

Abstract: Disclosed herein is a method of optical pulse emission including three phases. During a first phase, a capacitor is charged from a supply voltage node. During a second phase, a voltage stored on the capacitor is boosted, and then the capacitor is at least partially discharged through a light emitting device. During a third phase, the capacitor is further discharged by bypassing the light emitting device. The third phase may begin prior to an end of the second phase.

Abstract: A charge pump circuit includes a first charge pump stage circuit coupled in series with a second charge pump stage circuit. A discharge circuit operates to discharge the charge pump circuit. The discharge circuit includes: a first switched circuit coupled to a first output of the first charge pump stage circuit and configured, when actuated, to discharge the first output; and a second switched circuit coupled to a second output of the second charge pump stage circuit and configured, when actuated, to discharge the second output. A discharge control circuit actuates the first switched discharge circuit to discharge the first output and then, after the first output is fully discharged, actuates the second switched discharge circuit to discharge the second output.

Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.

Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.

Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

Abstract: Disclosed herein is a single integrated circuit chip with a main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. The safety area is internally powered by an internal regulated voltage generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage while protecting against shorts of the external line delivering the external voltage. The safety area includes protection circuits that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits serving to protect against shorts of the external line delivering the external analog signals.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.