Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

Abstract: A first node of converter circuit receives an input, provides an output at a second node, and has a third node coupled by an inductance to ground. A first switch has a current path between the first and third nodes and a second switch has a current path between the third and second nodes. The converter circuit operates in a first state (with the first switch conductive and the second switch non-conductive) and a second state (with the first switch non-conductive and the second switch conductive). Current flowing through the first switch is sensed during the first state to produce a sensing signal indicative of inductance current. The sensing signal is averaged to produce an averaged sensing signal indicative of an average value of the current. The averaged sensing signal is then weighted by a time during which the second switch is conductive to produce a weighted signal.

Abstract: A photonic system includes a first photonic circuit having a first face and a second photonic circuit having a second face. The first photonic circuit comprises first wave guides, and, for each first wave guide, a second wave guide covering the first wave guide, the second wave guides being in contact with the first face and placed between the first face and the second face, the first wave guides being located on the side of the first face opposite the second wave guides. The second photonic circuit comprises, for each second wave guide, a third wave guide covering the second wave guide. The first photonic circuit comprises first positioning devices projecting from the first face and the second photonic circuit comprises second positioning devices projecting from the second face, at least one of the first positioning devices abutting one of the second positioning devices in a first direction.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

Abstract: A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Abstract: A microfluidic valve formed in a body having a first and a second surface; an inlet channel extending in the body from the second surface; a first transverse channel extending in the body in a transverse direction with respect to the inlet channel; and an outlet channel extending in the body from the first surface. The inlet channel, the first transverse channel and the outlet channel form a fluidic path. The microfluidic valve further has an occluding portion, formed by the body and extending over the transverse channel; and a piezoelectric actuator coupled to the occluding portion and configured to move the occluding portion from an opening position of the valve, where the occluding portion does not interfere with the fluidic path, and a closing position of the valve, where the occluding portion interferes with and interrupts the fluidic path.

Abstract: A circuit includes comparator circuitry to sense a current through a load and compare the intensity of the current with a comparison threshold which can be set to a first, lower threshold value and a second, higher threshold value. Logic circuitry receives from the comparator circuitry a comparison signal having a first value or a second value based on whether the intensity is lower or higher than the comparison threshold. The logic circuitry is configured to assert a first overcurrent event signal or a second overcurrent event signal based on the comparison signal having the first value or the second value and the comparison threshold set to the first or second threshold value.

Abstract: An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.

Abstract: A leadframe for semiconductor devices, the leadframe comprising a die pad portion having a first planar die-mounting surface and a second planar surface opposed the first surface, the first surface and the second surface having facing peripheral rims jointly defining a peripheral outline of the die pad wherein the die pad comprises at least one package molding compound receiving cavity opening at the periphery of said first planar surface.

Abstract: An embodiment subscriber identification module includes a first communication interface, including first pads intended to be coupled to a modulator-demodulator circuit; a second interface, including second pads intended to be coupled to a subscriber identification module card; and a switching circuit, configured to couple the first pads to the second pads or to a communication module integrated to the subscriber identification module. Another embodiment concerns a method of controlling the module.

Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.

Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

Abstract: Described herein is an electronic device, including a pixel and a turn-off circuit. The pixel includes a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage node and an anode selectively coupled to ground through an enable circuit, and a clamp diode having an anode coupled to the anode of the SPAD and a cathode coupled to a turn-off voltage node. The turn-off circuit includes a sense circuit coupled between the turn-off voltage node and ground and configured to generate a feedback voltage, and a regulation circuit configured to sink current from the turn-off voltage node to ground based upon the feedback voltage such that a voltage at the turn-off voltage node maintains generally constant.

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.