Patents Assigned to Sumco Corporation
  • Patent number: 10718720
    Abstract: A method of evaluating a semiconductor wafer, which has a polished surface, by using a laser surface-inspection device including light-incident and light-receiving systems, includes evaluating the semiconductor wafer by detecting, as a light point defect, an abnormality of a process-induced defect and a surface-adhered foreign matter present on the polished surface of the semiconductor wafer, on the basis of measurement result obtained by directing incident light to the polished surface of the semiconductor wafer from one light-incident system and receiving, with a first light-receiving system, radiation light which has been radiated by the incident light being reflected or scattered by the polished surface, measurement result obtained by receiving the radiation light with a second light-receiving system, and measurement result obtained by receiving the radiation light with a third light-receiving system, and at least one of a light-receiving angle and polarization selectivity differs among the first, second
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: July 21, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Keiichiro Mori
  • Patent number: 10718722
    Abstract: Provided is a method of inspecting the back surface of an epitaxial wafer, capable of detecting pin mark defects in the back surface of the epitaxial wafer and quantitatively evaluating the defect size of individual point defects of the pin mark defects. The method of inspecting the back surface of an epitaxial wafer includes an imaging step of consecutively taking partial images of the back surface while moving the optical system using the scanning unit; an acquisition step of acquiring a full image of the back surface from the partial images; a detection step of detecting, in the full image, pin mark defects constituted by a set of a plurality of point defects present in the back surface of the silicon wafer 1; and a digitalization step of digitalizing the individual point defects to calculate the defect area of the individual point defects of the detected pin mark defects.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: July 21, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Keiko Matsuo, Naoyuki Wada, Masahiko Egashira
  • Publication number: 20200224327
    Abstract: Provided is a heat shielding member, a single crystal pulling apparatus, and a method of producing a single crystal silicon ingot, which can expand the margin of the crystal pulling rate with which a defect-free single crystal silicon can be obtained. A heat shielding member is provided in a single crystal pulling apparatus, the heat shielding member including a cylindrical tubular portion surrounding an outer circumferential surface of the single crystal silicon ingot; and a ring-shaped projecting portion under the tubular portion. The projecting portion has an upper wall, a bottom wall, and two vertical walls, a heat insulating material with a ring shape is provided in the space surrounded by those walls; and a gap between the vertical wall adjacent to the single crystal silicon ingot and the heat insulating material.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 16, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Kaoru KAJIWARA, Ryota SUEWAKA, Shunji KURAGAKI, Kazumi TANABE
  • Publication number: 20200224329
    Abstract: An n-type silicon single crystal production method of pulling up a silicon single crystal from a silicon melt containing red phosphorus as a principal dopant and growing the silicon single crystal by the Czochralski process, the method including: controlling electrical resistivity at a start position of a straight body portion of the silicon single crystal to 0.80 m?cm or more and 1.05 m?cm or less; and sequentially lowering the electrical resistivity of the silicon single crystal as the silicon single crystal is up and grown, thereby adjusting electrical resistivity of a part of the silicon single crystal to 0.5 m?m or more and less than 0.6 m?cm.
    Type: Application
    Filed: March 29, 2018
    Publication date: July 16, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Koichi MAEGAWA, Yasuhito NARUSHIMA, Yasufumi KAWAKAMI, Fukuo OGAWA, Yuuji TSUTSUMI
  • Patent number: 10711368
    Abstract: A manufacturing method of monocrystalline silicon includes: melting silicon housed in a quartz crucible into a silicon melt by heating the quartz crucible with a heating unit; dipping a seed crystal into the silicon melt in the quartz crucible to bring the seed crystal into contact with the silicon melt; and pulling up the seed crystal to grow monocrystalline silicon. In the pulling-up, a formation of a straight body of the monocrystalline silicon is started at a power consumption of the heating unit being equal to or more than 10000 kWh to grow an entirety of the monocrystalline silicon.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: July 14, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Tegi Kim
  • Patent number: 10710209
    Abstract: A wafer polishing apparatus is provided with a rotating platen to which a polishing pad is affixed and a polishing head that holds a wafer placed on the polishing pad while pressing the wafer. The polishing head has a membrane that contacts the upper surface of the wafer and applying a pressing force thereto and a support plate that supports the membrane. The membrane has a main surface part facing the bottom surface of the support plate and a side surface part facing the outer peripheral edge surface of the support plate. The vertical tension due to the side surface part of the membrane is larger than the lateral tension due to the main surface part of the membrane.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 14, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Ryoya Terakawa, Ryuichi Tanimoto, Hironori Kaneko
  • Publication number: 20200219929
    Abstract: A method of producing a semiconductor epitaxial wafer is provided. The method includes irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer in a surface portion of the semiconductor wafer, in which the modified layer includes a constituent element of the cluster ions in solid solution. The method further includes forming an epitaxial layer on the modified layer of the semiconductor wafer. The irradiating is performed such that a portion of the modified layer in a thickness direction becomes an amorphous layer, and an average depth of an amorphous layer surface from a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 9, 2020
    Applicant: SUMCO CORPORATION
    Inventor: Ryosuke OKUYAMA
  • Publication number: 20200199776
    Abstract: A production method of a monocrystalline silicon includes: growing the monocrystalline silicon pulled up from a silicon melt by the Czochralski process; and maintaining a pulling speed of the monocrystalline silicon when dislocations occur during pulling up of the monocrystalline silicon, so that the pulling up of the monocrystalline silicon is continued until a start point of the dislocations passes a temperature zone in which nuclei of oxygen precipitates form.
    Type: Application
    Filed: April 5, 2018
    Publication date: June 25, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Masao SAITOU, Kazuyuki EGASHIRA
  • Publication number: 20200203418
    Abstract: Provided is a semiconductor epitaxial wafer having metal contamination reduced by achieving higher gettering capability, a method of producing the semiconductor epitaxial wafer, and a method of producing a solid-state image sensing device using the semiconductor epitaxial wafer. The method of producing a semiconductor epitaxial wafer 100 includes a first step of irradiating a semiconductor wafer 10 containing at least one of carbon and nitrogen with cluster ions 16 thereby forming a modifying layer 18 formed from a constituent element of the cluster ions 16 contained as a solid solution, in a surface portion of the semiconductor wafer 10; and a second step of forming a first epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer 10.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 25, 2020
    Applicant: SUMCO Corporation
    Inventors: Takeshi Kadono, Kazunari Kurita
  • Publication number: 20200203178
    Abstract: Provided is a method of evaluating the impurity gettering capability of an epitaxial silicon wafer, which allows for very precise evaluation of the impurity gettering behavior of a modified layer formed immediately under an epitaxial layer, the modified layer containing carbon in solid solution. In this method, a modified layer located immediately under an epitaxial layer, the modified layer containing carbon in solid solution, is analyzed by three-dimensional atom probe microscopy, and the impurity gettering capability of the modified layer is evaluated based on a three-dimensional map of carbon in the modified layer, obtained by the analysis.
    Type: Application
    Filed: January 12, 2018
    Publication date: June 25, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Satoshi SHIGEMATSU, Ryosuke OKUYAMA, Kazunari KURITA
  • Publication number: 20200185215
    Abstract: Provided is a method of double-side polishing a silicon wafer using a double-side polishing apparatus, the method including in succession: a first polishing step of performing double-side polishing while supplying a first polishing agent that is an alkaline aqueous solution containing abrasive grains to the polishing cloths; a polishing agent switching step of stopping the supply of the first polishing agent and starting the supply of a second polishing agent that is an alkaline aqueous solution containing a water-soluble polymer with no abrasive grains, with the polishing cloths of the upper plate and the lower plate being in contact with the front surface and the back surface of the silicon wafer, respectively and with the upper plate and the lower plate being continuously rotated; and a second polishing step of performing double-side polishing while supplying the second polishing agent to the polishing cloths.
    Type: Application
    Filed: August 31, 2017
    Publication date: June 11, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Ryuichi TANIMOTO, Ichiro YAMAZAKI, Shunsuke MIKURIYA
  • Patent number: 10676840
    Abstract: The method is a method of evaluating a manufacturing process of a silicon material, wherein the manufacturing process includes a process that uses a member containing a carbon-containing sintered body, and the method of evaluating the manufacturing process of a silicon material includes performing DLTS measurement on a silicon material manufactured in the manufacturing process, and estimating a heavy metal contamination source of a silicon material manufactured in the manufacturing process with an indicator in the form of presence/absence of detection of a peak of a carbon-related level and presence/absence of detection of a peak of a heavy metal-related level in a DLTS spectrum obtained by the DLTS measurement.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 9, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Noritomo Mitsugi, Kazutaka Eriguchi, Shuichi Samata, Ayumi Masada
  • Publication number: 20200176461
    Abstract: A silicon wafer is capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer according to the present invention is a silicon wafer in which there is formed a multilayered film constituting a semiconductor device layer on one main surface thereof in a device process, which is warped in a bowl shape due to an isotropic film stress of the multilayered film, and which has a (111) plane orientation.
    Type: Application
    Filed: June 6, 2018
    Publication date: June 4, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Toshiaki ONO, Bong-Gyun KO
  • Publication number: 20200165742
    Abstract: A silicon single crystal manufacturing method by a Czochralski method pulls up a silicon single crystal from a silicon melt in a quartz crucible while applying a magnetic field to the silicon melt. During a pull-up process of the silicon single crystal, the surface temperature of the silicon melt is continuously measured, and crystal growth conditions are changed based on a result of frequency analysis of the surface temperature.
    Type: Application
    Filed: May 9, 2017
    Publication date: May 28, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Wataru SUGIMURA, Ryusuke YOKOYAMA, Mitsuaki HAYASHI
  • Publication number: 20200141024
    Abstract: In a producing method of an n-type monocrystalline silicon by pulling up a monocrystalline silicon from a silicon melt containing a main dopant in a form of red phosphorus to grow the monocrystalline silicon, the monocrystalline silicon exhibiting an electrical resistivity ranging from 0.5 m?cm to 1.0 m?cm is pulled up using a quartz crucible whose inner diameter ranges from 1.7-fold to 2.3-fold relative to a straight-body diameter of the monocrystalline silicon.
    Type: Application
    Filed: March 20, 2018
    Publication date: May 7, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Koichi MAEGAWA, Yasuhito NARUSHIMA, Yasufumi KAWAKAMI, Fukuo OGAWA, Ayumi KIHARA
  • Patent number: 10640883
    Abstract: After removing deposit on a susceptor in an epitaxial growth furnace by a cleaning recipe (step S101), a first epitaxial wafer is produced by growing an epitaxial layer on a first wafer based on a process recipe A (step S102). Subsequently, a step of producing an epitaxial wafer by growing an epitaxial layer on a wafer based on a process recipe B including second control parameters set such that the epitaxial wafer has approximately the same film thickness profile as the first wafer (step S103) is repeated a plurality of times to successively produce a plurality of epitaxial wafers (step S104). The cleaning recipe, the process recipe A, and the process recipe B repeated a plurality of times are carried out repeatedly (step S105).
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: May 5, 2020
    Assignee: SUMCO Corporation
    Inventors: Kenji Sakamoto, Masayuki Tsuji
  • Patent number: 10641708
    Abstract: Provided is a method of evaluating a semiconductor substrate, which evaluates quality of the semiconductor substrate by a photoluminescence measurement, wherein the evaluation by the photoluminescence measurement includes, after subjecting a surface of an evaluation-target semiconductor substrate to a pretreatment, irradiating the surface with excitation light, and then detecting emission obtained from the surface having been irradiated with the excitation light, and the pretreatment includes subjecting the surface of the evaluation-target semiconductor substrate to be irradiated with the excitation light to an oxide film formation treatment and charging the surface of the formed oxide film by corona discharge.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 5, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Kazutaka Eriguchi, Tsuyoshi Kubota
  • Publication number: 20200135460
    Abstract: A production method of a monocrystalline silicon includes adding red phosphorus in a silicon melt so that an electrical resistivity of the monocrystalline silicon falls in a range of 0.5 m?·cm or more and less than 0.7 m?·cm; and pulling up the monocrystalline silicon so that a time for a temperature of at least a part of a straight body of the monocrystalline silicon to be within a range of 570 degrees C. 70 degrees C. is in a range from 10 minutes to 50 minutes.
    Type: Application
    Filed: April 12, 2018
    Publication date: April 30, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Yasuhito NARUSHIMA, Koichi MAEGAWA, Fukuo OGAWA, Yasufumi KAWAKAMI
  • Publication number: 20200127043
    Abstract: The present invention provides a method of producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. The method of producing a semiconductor epitaxial wafer includes a first step of irradiating a surface portion 10A of a semiconductor wafer 10 with cluster ions 16 thereby forming a modifying layer 18 formed from carbon and a dopant element contained as a solid solution that are constituent elements of the cluster ions 16, in the surface portion 10A of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer, the epitaxial layer 20 having a dopant element concentration lower than the peak concentration of the dopant element in the modifying layer 18.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Applicant: SUMCO Corporation
    Inventors: Takeshi Kadono, Kazunari Kurita
  • Publication number: 20200126796
    Abstract: Provided is a semiconductor epitaxial wafer in which the concentration of hydrogen in a modifying layer can be maintained at a high level and the crystallinity of an epitaxial layer is excellent. A semiconductor epitaxial wafer has a semiconductor wafer, a modifying layer formed in a surface portion of the semiconductor wafer, which modifying layer has hydrogen contained as a solid solution in the semiconductor wafer, and an epitaxial layer formed on the modifying layer. The concentration profile of hydrogen in the modifying layer in the thickness direction from a surface of the epitaxial layer is a double peak concentration profile including a first peak shallower in the depth direction and a second peak deeper in the depth direction.
    Type: Application
    Filed: June 12, 2018
    Publication date: April 23, 2020
    Applicant: SUMCO CORPORATION
    Inventor: Ryosuke OKUYAMA