Abstract: An epitaxial wafer that includes a silicon wafer and an epitaxial layer on the silicon wafer. The silicon wafer contains hydrogen that has a concentration profile including a first peak and a second peak. A hydrogen peak concentration of the first peak and a hydrogen peak concentration of the second peak are each not less than 1×1017 atoms/cm3.
Abstract: Provided is a method of double-side polishing a silicon wafer using a double-side polishing apparatus, the method including in succession: a first polishing step of performing double-side polishing while supplying a first polishing agent that is an alkaline aqueous solution containing abrasive grains to the polishing cloths; a polishing agent switching step of stopping the supply of the first polishing agent and starting the supply of a second polishing agent that is an alkaline aqueous solution containing a water-soluble polymer with no abrasive grains, with the polishing cloths of the upper plate and the lower plate being in contact with the front surface and the back surface of the silicon wafer, respectively and with the upper plate and the lower plate being continuously rotated; and a second polishing step of performing double-side polishing while supplying the second polishing agent to the polishing cloths.
Abstract: In an exemplary embodiment, a quartz glass crucible 1 includes: a cylindrical crucible body 10 which has a bottom and is made of quartz glass; and a first crystallization-accelerator-containing coating film 13A which is formed on an inner surface 10a so as to cause an inner crystal layer composed of an aggregate of dome-shaped or columnar crystal grains to be formed on a surface-layer portion of the inner surface 10a of the crucible body 10 by heating during a step of pulling up the silicon single crystal by a Czochralski method. The quartz glass crucible is capable of withstanding a single crystal pull-up step undertaken for a very long period of time.
Type:
Grant
Filed:
August 24, 2017
Date of Patent:
November 2, 2021
Assignee:
SUMCO CORPORATION
Inventors:
Hiroshi Kishi, Kouta Hasebe, Takahiro Abe, Hideki Fujiwara
Abstract: A polishing head of a wafer polishing apparatus is provided with: a membrane head that can independently control a center control pressure pressing a center portion of a wafer, and an outer periphery control pressure pressing an outer peripheral portion of the wafer; an outer ring integrated with the membrane head so as to configure the outer peripheral portion of the membrane head; and a contact type retainer ring provided outside the membrane head. The membrane head has a central pressure chamber of a single compartment structure that controls the center control pressure, and an outer peripheral pressure chamber that is provided above the central pressure chamber, and that controls the outer periphery control pressure. A position of a lower end of the outer ring reaches at least a position of an inner bottom surface of the central pressure chamber.
Abstract: The sample introduction device includes a nebulizer that atomizes a sample liquid; a spray chamber that has one end into which a spray port part of the nebulizer is inserted and the other end from which at least a part of liquid droplets of the sample liquid sprayed from the spray port part is discharged to an outside; and a heating electromagnetic wave radiation unit that is arranged outside the spray chamber, wherein the heating electromagnetic wave radiation unit performs radiation of heating electromagnetic waves from the outside of the spray chamber toward at least a part of the spray chamber other than a part into which the spray port part of the nebulizer is inserted.
Type:
Application
Filed:
April 20, 2021
Publication date:
October 28, 2021
Applicants:
SUMCO CORPORATION, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
Abstract: Provided is a method of chamfer machining a silicon wafer which makes it possible to increase the number of machining operations that can be performed using a chamfering wheel used for helical chamfer machining in the case of obtaining a small finished wafer taper angle. The method in which helical chamfer machining is performed so that the finished wafer taper angle ? of an edge portion in the one silicon wafer is within an allowable angle range of a target wafer taper angle ?0 includes a first truing step; a first chamfer machining step; a step of determining a groove bottom diameter ?A of the fine grinding grindstone portion; a second truing step using a second truer taper angle ?2; and a second chamfer machining step. The second truer taper angle ?2 is made larger than the first truer taper angle ?1.
Abstract: For correction of a source gas supply time and a dopant gas flow rate, a calculation unit in an epitaxial wafer production system performs not only correction based on a result of comparing measured thickness and resistivity of an epitaxial film respectively with a target thickness range and a target resistivity range, but also correction based on a variation in total output value of upper and lower lamps.
Abstract: A silicon wafer having a layer of oxygen precipitates and method of manufacturing thereof wherein the wafer exhibiting robustness characterized as having a ratio of a first average density from a first treatment that to a second average density from a second treatment is between 0.74 to 1.02, wherein the first treatment includes heating the wafer or a portion of the wafer at about 1150° C. for about 2 minutes and then between about 950 to 1000° C. for about 16 hours, and the second treatment includes heating the wafer or a portion of the wafer at about 780° C. for about 3 hours and then between about 950 to 1000° C. for about 16 hours. The wafer exhibits heretofore unattainable uniformity wherein a ratio of an oxygen precipitate density determined from any one cubic centimeter in the BMD layer of the wafer to another oxygen precipitate density from any other one cubic centimeter in the BMD layer of the wafer is in a range of 0.77 to 1.30.
Abstract: Provided a method of producing a carrier which make it possible to prevent the reduction in the flatness of a semiconductor wafer even if the semiconductor wafer is subjected to repeated double-side polishing procedures. The method of producing a carrier including a metal portion and a ring-shaped resin portion includes: a preparation step of preparing the metal portion and the resin portion (Step S1); a placement step of placing the resin portion in the retainer opening in the metal portion (Step S2); and a resin portion polishing step of polishing both surface of the resin portion (Step S4). The method includes, prior to the resin portion polishing step (Step S4), a production stage swelling step of swelling the resin portion placed in the retainer opening in the metal portion by impregnating the resin portion with a first liquid (Step S3).
Abstract: Provided is a method of evaluating cleanliness of a member having a silicon carbide surface, the method including bringing the silicon carbide surface into contact with a mixed acid of hydrofluoric acid, hydrochloric acid and nitric acid; concentrating the mixed acid brought into contact with the silicon carbide surface by heating; subjecting a sample solution obtained by diluting a concentrated liquid obtained by the concentration to quantitative analysis of metal components by Inductively Coupled Plasma-Mass Spectrometry; and evaluating cleanliness of the member having a silicon carbide surface on the basis of a quantitative result of metal components obtained by the quantitative analysis.
Abstract: Provided is a method of accurately predicting the thermal donor formation behavior in a silicon wafer, a method of evaluating a silicon wafer using the prediction method, and a method of producing a silicon wafer using the evaluation method. The method of predicting the formation behavior of thermal donors, includes: a first step of setting an initial oxygen concentration condition before performing heat treatment on the silicon wafer for reaction rate equations based on both a bond-dissociation model of oxygen clusters associated with the diffusion of interstitial oxygen and a bonding model of oxygen clusters associated with the diffusion of oxygen dimers; a second step of calculating the formation rate of oxygen clusters formed through the heat treatment using the reaction rate equations; and a third step of calculating the formation rate of thermal donors formed through the heat treatment based on the formation rate of the oxygen clusters.
Type:
Grant
Filed:
June 12, 2018
Date of Patent:
September 14, 2021
Assignee:
SUMCO Corporation
Inventors:
Kazuhisa Torigoe, Shigeru Umeno, Toshiaki Ono
Abstract: Provided is a method for cleaning a semiconductor wafer which can effectively reduce deposits on a main surface of a wafer. A method for cleaning a semiconductor wafer of the present disclosure includes supplying ozone water into a cleaning tank from a lower part of the cleaning tank with the ozone water overflowing from the upper part of the cleaning tank to outside the cleaning tank (first step), subsequently, stopping a supply of the ozone water (second step), subsequently, immersing a semiconductor wafer into the ozone water in the cleaning tank (third step), and subsequently, resupplying the ozone water into the cleaning tank from the lower part of the cleaning tank with the ozone water overflowing again from the upper part of the cleaning tank to outside the cleaning tank (fourth step).
Abstract: A method for measuring carbon concentration in silicon single crystal according to the present invention includes a step of measuring a carbon concentration of a sample of silicon single crystal using FT-IR, a step of measuring a temperature of the sample during, prior to, or after the measurement of the carbon concentration of the sample, and steps of correcting a measured value Ycs of the carbon concentration of the sample based on the measuring temperature of the sample when the measured Ycs value of the carbon concentration of the sample is at or below 0.5×1016 atoms/cm3.
Abstract: Provided is a semiconductor epitaxial wafer in which the concentration of hydrogen in a modifying layer can be maintained at a high level and the crystallinity of an epitaxial layer is excellent. A semiconductor epitaxial wafer has a semiconductor wafer, a modifying layer formed in a surface portion of the semiconductor wafer, which modifying layer has hydrogen contained as a solid solution in the semiconductor wafer, and an epitaxial layer formed on the modifying layer. The concentration profile of hydrogen in the modifying layer in the thickness direction from a surface of the epitaxial layer is a double peak concentration profile including a first peak shallower in the depth direction and a second peak deeper in the depth direction.
Abstract: Provided is a method capable of predicting the warpage caused when a silicon wafer is subjected to heat treatment taking into account the effect of oxygen and a method of producing a silicon wafer. The method includes: determining the mobile dislocation density, the stress, and the time evolution of the strain of the silicon wafer being subjected to heat treatment from the rate of change in the strain and the rate of change in the mobile dislocation density; and determining the magnitude of plastic deformation of the silicon wafer as a warpage. The mobile dislocation density Ni at the start of the heat treatment is given as: Ni=A×(?Oi×L?Lo)2.5??(1), where A and L0: constants, ?Oi: the concentration of oxygen used by oxygen precipitates in the silicon wafer at the start of the heat treatment, L: the mean size of the oxygen precipitates at the start of the heat treatment.
Abstract: A silicon wafer having a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 ?m to 285 ?m from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.?X?1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec. The time Y and the temperature X satisfy Y=7.88×1067×X?22.5.
Abstract: Provided is a double-side polishing apparatus and a double-side polishing method for a work which make it possible to terminate double-side polishing with timing allowing a work having been polished to have a target shape. A computing unit performs a step of grouping the data of thicknesses on a work basis; a step of extracting shape components of each work; a step of identifying a position of each of the shape components in the work radial direction; a step of computing a shape distribution of the work; a step of obtaining a shape index of the work; and a step of determining timing at which the obtained shape index becomes a set value of the shape index, determined based on a difference between a target value and an actual value of the shape index in the previous batch, as timing of termination of the double-side polishing.
Abstract: Provided is a method of producing a high resistance n-type silicon single crystal ingot with small tolerance margin on resistivity in the crystal growth direction, which is suitably used in a power device. In the method of producing a silicon single crystal ingot using Sb or As as an n-type dopant, while a silicon single crystal ingot is pulled up, the amount of the n-type dopant being evaporated from a silicon melt per unit solidification ratio is kept within a target evaporation amount range per unit solidification ratio by controlling one or more pulling condition values including at least one of the pressure in a chamber, the flow volume of Ar gas, and a gap between a guide portion and the silicon melt.
Abstract: A wafer polishing method of applying mirror polishing to a surface of a wafer using a wafer polishing apparatus provided with a multi-zone pressurizing polishing head having a wafer pressing surface divided into a plurality of pressure zones and capable of performing pressurizing control independently for each pressure zone is provided with a measurement step of measuring a nanotopography map on the wafer surface; and a polishing step of performing the polishing by setting the polishing pressure of the polishing head against the wafer for each pressure zone based on a result of the measurement of the nanotopography map.
Abstract: A manufacturing method allows growth of a group III nitride semiconductor layer on a Si substrate with an AlN buffer layer interposed between same, so as to suppress group III material from diffusing into the Si substrate. The group III nitride semiconductor substrate manufacturing method includes: a step of forming an AlN coating on the inside of a furnace; steps of installing an Si substrate in the furnace covered with the AlN coating and forming an AlN buffer layer on the Si substrate; and a step of forming a group III nitride semiconductor layer on the AN buffer layer.
Type:
Application
Filed:
March 5, 2019
Publication date:
July 8, 2021
Applicant:
SUMCO CORPORATION
Inventors:
Koji MATSUMOTO, Toshiaki ONO, Hiroshi AMANO, Yoshio HONDA