Patents Assigned to Sumco Corporation
  • Publication number: 20200373208
    Abstract: Provided is a method of measuring the concentration of Fe in a p-type silicon wafer by an SPV method enabling improvement in the measurement accuracy for Fe concentrations of 1×109/cm3 or less. The method of measuring the concentration of Fe in a p-type silicon wafer includes measuring an Fe concentration in the p-type silicon wafer based on measurement using an SPV method. The measurement is performed in an atmosphere in which the total concentration of Na+, NH4+, and K+ is 1.750 ?g/m3 or less, and the total concentration of F?, Cl?, NO2?, PO43?, Br?, NO3?, and SO42? is 0.552 ?g/m3 or less.
    Type: Application
    Filed: October 2, 2018
    Publication date: November 26, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Shinya FUKUSHIMA, Takehiro TSUNEMORI
  • Publication number: 20200373158
    Abstract: The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions containing carbon, phosphorus, and hydrogen as constituent elements to form a modified layer that is located in a surface layer portion of the semiconductor wafer and that contains the constituent elements of the cluster ions as a solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The ratio y/x of the number y of the phosphorus atoms with respect to the number x of the carbon atoms satisfies 0.5 or more and 2.0 or less, where the number of atoms of carbon, phosphorus, and hydrogen in the cluster ions is expressed by CxPyHz (x, y, and z are integers each equal to or more than 1).
    Type: Application
    Filed: January 8, 2019
    Publication date: November 26, 2020
    Applicant: SUMCO CORPORATION
    Inventor: Ryosuke OKUYAMA
  • Publication number: 20200365387
    Abstract: Provided a method of producing a carrier which make it possible to prevent the reduction in the flatness of a semiconductor wafer even if the semiconductor wafer is subjected to repeated double-side polishing procedures. The method of producing a carrier including a metal portion and a ring-shaped resin portion includes: a preparation step of preparing the metal portion and the resin portion (Step S1); a placement step of placing the resin portion in the retainer opening in the metal portion (Step S2); and a resin portion polishing step of polishing both surface of the resin portion (Step S4). The method includes, prior to the resin portion polishing step (Step S4), a production stage swelling step of swelling the resin portion placed in the retainer opening in the metal portion by impregnating the resin portion with a first liquid (Step S3).
    Type: Application
    Filed: August 14, 2018
    Publication date: November 19, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Shunsuke MIKURIYA, Tomonori MIURA
  • Publication number: 20200365472
    Abstract: Provided is a method of evaluating a silicon wafer manufacturing process for mass-producing multiple silicon wafers. Lifetime measurement to silicon wafers mass-produced in the silicon wafer manufacturing process is performed in different locations within a surface of each of the silicon wafers and multiple measurement values are obtained. The representative value is determined for each of the silicon wafers from the multiple measurement values. The determination threshold is obtained for each wafer group including multiple silicon wafers using the representative value for each of the silicon wafers included in the wafer group. Whether the wafer group includes a silicon wafer having a lifetime outlier determined on the basis of the determination threshold among the multiple measurement values obtained for each of the silicon wafers is determined, and whether the manufacturing process may cause a defective product to be produced is determined.
    Type: Application
    Filed: July 2, 2018
    Publication date: November 19, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Shigeru DAIGO, Shuhei MATSUDA
  • Publication number: 20200353585
    Abstract: Provided is a method of double-side polishing a wafer by which variations of the GBIR values of polished wafers between batches can be reduced. In the method of double-side polishing a wafer, a current batch includes measuring the center thickness of the wafer before polishing (S100); setting a target GBIR value within a predetermined range (S110); calculating a polishing time of the current batch based on Formula (1) (S120); and polishing both surfaces of the wafer for the calculated polishing time (S130). Polishing time of current batch=polishing time of previous batch+A1×(center thickness of wafer before polishing in previous batch?center thickness of wafer before polishing in current batch)+A2×(GBIR value of wafer after polishing in previous batch?target GBIR value)+A3??(1), where A1, A2, and A3 are predetermined coefficients.
    Type: Application
    Filed: October 23, 2018
    Publication date: November 12, 2020
    Applicant: SUMCO CORPORATION
    Inventor: Yuji MIYAZAKI
  • Publication number: 20200354853
    Abstract: An epitaxial growth apparatus that can provide an improved thickness uniformity of an epitaxial film is provided. An epitaxial growth apparatus in accordance with the present disclosure includes a susceptor 20 and a preheat ring 60 surrounding a side of the susceptor 20 having a gap interposed therebetween. A width of the gap at least in part between the susceptor 20 and the preheat ring 60 is set to be longer than a width w1 of the gap between the susceptor 20 and the preheat ring 60 in the vicinity of the reactant gas inlet.
    Type: Application
    Filed: March 1, 2018
    Publication date: November 12, 2020
    Applicant: SUMCO CORPORATION
    Inventor: Haku KOMORI
  • Publication number: 20200346258
    Abstract: A cleaning method includes a first removal step of causing an inert gas to which a pulsation is applied to flow into an exhaust pipe after a silicon single crystal doped with an n-type dopant is produced, to peel and remove a deposit; and a second removal step of causing an atmospheric air to which no pulsation is applied to flow into the exhaust pipe through a chamber to burn a part of the deposit with the atmospheric air, the part being not removable in the first removal step, and peel and remove a burned substance of the deposit.
    Type: Application
    Filed: November 16, 2018
    Publication date: November 5, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Koichi MAEGAWA, Takuya YOTSUI, Satoru HAMAKAWA
  • Publication number: 20200346319
    Abstract: Provided is a double-side polishing apparatus and a double-side polishing method which make it possible to terminate double-side polishing with timing allowing a work having been polished to have a target shape. A computing unit 13 performs a step of grouping the data of thicknesses measured using work thickness measuring devices 11 on a work basis; a step of extracting shape components of each work from the thickness data; a step of identifying a position of each of the shape components in the work radial direction; a step of computing a shape distribution of the work from the identified position ; a step of obtaining a shape index of the work from the computed shape distribution; and a step of determining timing of termination of the double-side polishing based on the obtained shape index, thus timing of termination of the double-side polishing is determined.
    Type: Application
    Filed: October 22, 2018
    Publication date: November 5, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Mami KUBOTA, Keiichi TAKANASHI
  • Patent number: 10822717
    Abstract: A seed crystal holder for pulling up a single crystal is made of a carbon fiber-reinforced carbon composite material, and has a substantially cylindrical shape with a hollow space having a shape matching an outer shape of a substantially rod-shaped seed crystal. A direction of carbon fibers at a part in contact with at least an outer peripheral surface of the seed crystal has isotropy as viewed from a central axis of the hollow space.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 3, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Eiichi Kawasaki
  • Patent number: 10822716
    Abstract: In an exemplary embodiment, a quartz glass crucible 1 includes: a high-aluminum-content layer 14B which is made of quartz glass having a relatively high average aluminum concentration and is provided to form an outer surface 10b of the quartz glass crucible 1; and a low-aluminum-content layer 14A which is made of quartz glass having a lower average aluminum concentration than that of the high-aluminum-content layer 14B and is provided on an inner side of the high-aluminum-content layer 14B, wherein the low-aluminum-content layer 14A includes an opaque layer 11 made of quartz glass containing a large number of minute bubbles, and the high-aluminum-content layer 14B is made of transparent or translucent quartz glass having a lower bubble content than that of the opaque layer 11. The quartz glass crucible is capable of withstanding a single crystal pull-up step undertaken for a very long period of time.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 3, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Hiroshi Kishi, Masanori Fukui
  • Publication number: 20200343130
    Abstract: In a method of producing a bonded wafer, the amount of depression of the polishing cloth is 50 ?m to 90 ?m, and the surface hardness (ASKER C) of the polishing cloth is 50 to 60. In the bonded wafer, the polycrystalline silicon layer has a thickness variation ?t of 5% or less, and the support substrate wafer has a GBIR of 0.2 ?m or less and an SFQR of 0.06 ?m or less after the polycrystalline silicon layer is polished.
    Type: Application
    Filed: January 8, 2019
    Publication date: October 29, 2020
    Applicant: SUMCO Corporation
    Inventors: Youzou SATOU, Kazuaki KOZASA
  • Publication number: 20200343149
    Abstract: Provided is a method of evaluating a silicon layer, including forming an oxide film on a surface of a silicon layer, performing a charging treatment of charging a surface of the formed oxide film to a negative charge, and measuring a resistivity of the silicon layer that has been subjected to the charging treatment by a van der Pauw method.
    Type: Application
    Filed: January 18, 2019
    Publication date: October 29, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Sayaka MAKISE, Shuichi SAMATA, Noritomo MITSUGI, Sumio MIYAZAKI
  • Publication number: 20200306922
    Abstract: In a method of polishing a silicon wafer, a final polishing step includes an upstream polishing step and a subsequent finish polishing step. In the upstream polishing step, as a polishing agent, a first alkaline aqueous solution containing abrasive grains with a density of 1×1014/cm3 or more is first supplied, and the supply is then switched to a supply of a second alkaline aqueous solution containing a water-soluble polymer and abrasive grains with a density of 5×1013/cm3 or less. In the finish polishing step, as a polishing agent, a third alkaline aqueous solution containing a water-soluble polymer and abrasive grains with a density of 5×10?13/cm3 or less is supplied. Thus, the formation of not only PIDs but also scratches with small depth can be suppressed.
    Type: Application
    Filed: October 17, 2017
    Publication date: October 1, 2020
    Applicant: SUMCO CORPORATION
    Inventor: Shuhei MATSUDA
  • Patent number: 10777704
    Abstract: A manufacturing method for a group III nitride semiconductor substrate is provided with a first step of forming a second group III nitride semiconductor layer on a substrate; a second step of forming a protective layer on the second group III nitride semiconductor layer; a third step of selectively forming pits on dislocation portions of the second group III nitride semiconductor layer by gas-phase etching applied to the protective layer and the second group III nitride semiconductor layer; and a fourth step of forming a third group III nitride semiconductor layer on the second group III nitride semiconductor layer and/or the remaining protective layer so as to allow the pits to remain.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 15, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Koji Matsumoto, Toshiaki Ono, Hiroshi Amano, Yoshio Honda
  • Publication number: 20200283925
    Abstract: A crucible-supporting pedestal includes a fitting recess portion into which a divided graphite member is fittable. An opening edge of the fitting recess portion is formed such that a contact area between the opening edge and the divided graphite member is provided at a position higher than a surface of a solidified product of a silicon melt which remains in a quartz crucible after a silicon single crystal is grown, and a force, which is applied to the divided graphite member by an expansion of the silicon melt when the silicon melt is solidified, is applied to a position lower than the contact area.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 10, 2020
    Applicant: SUMCO CORPORATION
    Inventor: Kenji MUNEZANE
  • Patent number: 10744616
    Abstract: A wafer polishing method of polishing one surface of a wafer by rotating a rotating platen to which a polishing pad is affixed and a pressurizing head while supplying slurry onto the rotating platen and pressurizing/holding the wafer on the polishing pad with the pressurizing head, the method including: calculating an F/T value by monitoring a load current value F of a motor for rotating the rotating platen and a surface temperature T of the polishing pad during the wafer polishing; and controlling at least one of the rotation speed of the rotating platen and the polishing pressure of the pressurizing head based on the calculated F/T value.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: August 18, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Tomonori Kawasaki, Ryoya Terakawa
  • Publication number: 20200258735
    Abstract: A wafer polishing method according to the present invention is provided with: a first polishing step (step S1) of polishing a wafer using a polishing head of an independent pressurizing system having a retainer ring capable of performing pressing operation independently of a wafer pressurizing mechanism; and a second polishing step (step S3) of polishing the wafer that has been polished in the first polishing step using a polishing head of a fixed pressurizing system having a retainer ring fixed to the wafer pressurizing mechanism.
    Type: Application
    Filed: November 4, 2016
    Publication date: August 13, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Takashi NISHITANI, Ryuichi TANIMOTO, Ryoya TERAKAWA
  • Patent number: 10727071
    Abstract: Provided is a method of analyzing metal contamination of a silicon wafer, the method including etching a surface layer region of the silicon wafer by bringing a surface of a silicon wafer to be analyzed into contact with etching gas that includes hydrogen fluoride gas and nitric acid gas; bringing an exposed surface of the silicon wafer, exposed by the etching, into contact with gas generated from a mixed acid including hydrochloric acid and nitric acid; heating the silicon wafer that has been brought into contact with the gas generated from the mixed acid; bringing the exposed surface, exposed by the etching, of the silicon wafer after the heating into contact with a recovery solution; and analyzing a metal component in the recovery solution that has been brought into contact with the exposed surface, exposed by the etching, of the silicon wafer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 28, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Taisuke Mizuno
  • Patent number: 10724150
    Abstract: A method of manufacturing a single crystal is provided with a raw material melting step of heating a silicon raw material in a quartz crucible using a carbon heater to generate a silicon melt; and a crystal pull-up step of pulling up a single crystal from the silicon melt generated by the raw material melting step, wherein the silicon raw material is heated with the maximum surface temperature of a first part of the heater that is positioned above at least the upper end of the quartz crucible maintained below 1500° C. in the raw material melting step.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: July 28, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Kaoru Kajiwara, Ryota Suewaka, Hideki Tanaka, Takahiro Kanehara
  • Patent number: 10718720
    Abstract: A method of evaluating a semiconductor wafer, which has a polished surface, by using a laser surface-inspection device including light-incident and light-receiving systems, includes evaluating the semiconductor wafer by detecting, as a light point defect, an abnormality of a process-induced defect and a surface-adhered foreign matter present on the polished surface of the semiconductor wafer, on the basis of measurement result obtained by directing incident light to the polished surface of the semiconductor wafer from one light-incident system and receiving, with a first light-receiving system, radiation light which has been radiated by the incident light being reflected or scattered by the polished surface, measurement result obtained by receiving the radiation light with a second light-receiving system, and measurement result obtained by receiving the radiation light with a third light-receiving system, and at least one of a light-receiving angle and polarization selectivity differs among the first, second
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: July 21, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Keiichiro Mori