Patents Assigned to Sumco Corporation
  • Patent number: 10910328
    Abstract: Provided is a silicon wafer manufacturing method capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer manufacturing method according to the present invention is provided with calculating a target thickness of the silicon wafer required for ensuring a warpage reduction amount of a silicon wafer warped during a device process from a relationship between an amount of warpage of a silicon wafer and a thickness thereof occurring due to application of the same film stress to a plurality of silicon wafers having mutually different thicknesses; and processing a silicon single crystal ingot to thereby manufacture silicon wafers having the target thickness.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: February 2, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Bong-Gyun Ko, Toshiaki Ono
  • Publication number: 20210028023
    Abstract: The method of etching a boron-doped p-type silicon wafer includes preparing an etching gas by introducing an ozone-containing gas and hydrofluoric acid mist into a chamber and mixing them; and performing gas phase decomposition of a surface layer area of a boron-doped p-type silicon wafer with a resistivity of 0.016 ?cm or less by bringing the etching gas into contact with a surface of the boron-doped p-type silicon wafer; and further includes introducing the ozone-containing gas into the chamber at a flow rate of 3,000 sccm or more; and preparing the hydrofluoric acid mist by atomizing hydrofluoric acid with a hydrofluoric acid concentration of 41 mass % or more.
    Type: Application
    Filed: December 12, 2018
    Publication date: January 28, 2021
    Applicant: SUMCO CORPORATION
    Inventors: Hirokazu KATO, Takafumi YAMASHITA
  • Patent number: 10903099
    Abstract: Provided is a semiconductor wafer placement position determination method making it possible to measure a position deviation at a placement position of a semiconductor wafer when using a susceptor that is N-fold symmetric with respect to the center of the susceptor as a rotation axis. In this method, an opening edge of a counterbore portion of the susceptor is N-fold symmetric with respect to the center of the susceptor as a rotation axis (N?2). This method includes: a measurement step of measuring, while rotating the susceptor on which the semiconductor wafer is placed, a gap distance between a periphery of the semiconductor wafer and the opening edge; a first calculation step of performing, based on variation of the gap distance, period regression analysis; and a second calculation step of determining the position deviation based on an amplitude of a trigonometric function obtained by the first calculation step.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 26, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Ikuhiro Nakamura, Keiichi Takanashi
  • Patent number: 10895538
    Abstract: Provided is a method of preparing a sample surface on which a marking is formed, wherein the marking is a local oxide film locally formed on the sample surface, the local oxide film is formed by applying voltage between a probe and the sample surface while a tip of the probe is in contact with the sample surface, and the probe is brought into contact with the sample surface after moisture supply.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 19, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Keiichiro Mori, Kaori Hashimoto, Chie Hide
  • Patent number: 10895018
    Abstract: A production method of a monocrystalline silicon includes: forming a shoulder of the monocrystalline silicon; and forming a straight body of the monocrystalline silicon. To form the shoulder, a crucible is heated such that a heating ratio, which is calculated by dividing a volume of heat from a lower heater by a volume of heat from an upper heater, increases from a predetermined value of 1 or more.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: January 19, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Yasuhito Narushima, Toshimichi Kubota
  • Publication number: 20210010156
    Abstract: A seed crystal holder for pulling up a single crystal is made of a carbon fiber-reinforced carbon composite material, and has a substantially cylindrical shape with a hollow space having a shape matching an outer shape of a substantially rod-shaped seed crystal. A direction of carbon fibers at a part in contact with at least an outer peripheral surface of the seed crystal has isotropy as viewed from a central axis of the hollow space.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 14, 2021
    Applicant: SUMCO CORPORATION
    Inventor: Eiichi KAWASAKI
  • Publication number: 20200411391
    Abstract: A semiconductor wafer evaluation method includes acquiring a reflection image as a bright-field image by receiving reflected light which is obtained when irradiating one surface side of a semiconductor wafer to be evaluated with light; acquiring a scattered image as a dark-field image by receiving scattered light which is obtained when irradiating the surface side of the semiconductor wafer with light; and obtaining a distance between a bright zone that is observed in the reflection image and a bright zone that is observed in the scattered image. The semiconductor wafer to be evaluated is a semiconductor wafer in which a chamfered surface is formed in a wafer outer peripheral edge section, and the method includes evaluating a shape of a boundary part between a main surface on the surface side irradiated with the light of the semiconductor wafer to be evaluated and a chamfered surface adjacent to the main surface.
    Type: Application
    Filed: January 7, 2019
    Publication date: December 31, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Takahiro NAGASAWA, Yasuyuki HASHIMOTO, Hirotaka KATO
  • Publication number: 20200407875
    Abstract: A method of controlling a convection pattern of a silicon melt includes applying a horizontal magnetic field having an intensity of 0.2 tesla or more to the silicon melt in a rotating quartz crucible to fix a direction of a convection flow in a plane orthogonal to an application direction of the horizontal magnetic field in the silicon melt, the horizontal magnetic field being applied so that a central magnetic field line passes through a point horizontally offset from a center axis of the quartz crucible by 10 mm or more.
    Type: Application
    Filed: February 27, 2019
    Publication date: December 31, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Naoki MATSUSHIMA, Ryusuke YOKOYAMA, Hideki SAKAMOTO, Wataru SUGIMURA
  • Publication number: 20200407870
    Abstract: A method of estimating an oxygen concentration in monocrystalline silicon, which is pulled up by a pull-up device having a hot zone with a plane-asymmetric arrangement with respect to a plane defined by a crystal pull-up shaft and an application direction of a horizontal magnetic field, includes, in at least one of a neck-formation step or a shoulder-formation step for the monocrystalline silicon: a step of measuring a surface temperature of a silicon melt at a point defining a plane-asymmetric arrangement of a hot zone, and a step of estimating the oxygen concentration in a straight body of the pulled-up monocrystalline silicon based on the measured surface temperature of the silicon melt and a predetermined relationship between the surface temperature of the silicon melt and the oxygen concentration in the monocrystalline silicon.
    Type: Application
    Filed: February 27, 2019
    Publication date: December 31, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Shin MATSUKUMA, Kazuyoshi TAKAHASHI, Toshinori SEKI, Tegi KIM, Ryusuke YOKOYAMA
  • Publication number: 20200411392
    Abstract: Provided is a method capable of predicting the warpage caused when a silicon wafer is subjected to heat treatment taking into account the effect of oxygen and a method of producing a silicon wafer. The method includes: determining the mobile dislocation density, the stress, and the time evolution of the strain of the silicon wafer being subjected to heat treatment from the rate of change in the strain and the rate of change in the mobile dislocation density; and determining the magnitude of plastic deformation of the silicon wafer as a warpage. The mobile dislocation density Ni at the start of the heat treatment is given as: Ni=A×(?Oi×L?L0)2.5??(1), where A and L0: constants, ?Oi: the concentration of oxygen used by oxygen precipitates in the silicon wafer at the start of the heat treatment, L: the mean size of the oxygen precipitates at the start of the heat treatment.
    Type: Application
    Filed: May 21, 2018
    Publication date: December 31, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Bong-Gyun KO, Kousuke TAKATA
  • Publication number: 20200399780
    Abstract: A convection pattern estimation method of a silicon melt includes: applying a horizontal magnetic field of 0.2 tesla or more to a silicon melt in a rotating quartz crucible with use of a pair of magnetic bodies disposed across the quartz crucible; before a seed crystal is dipped into the silicon melt to which the horizontal magnetic field is applied; measuring temperatures at a first and second measurement points positioned on a first imaginary line that passes through a center of a surface of the silicon melt and is not in parallel with a central magnetic field line of the horizontal magnetic field as viewed vertically from above; and estimating a direction of a convection flow in a plane in the silicon melt orthogonal to the direction in which the horizontal magnetic field is applied on a basis of the measured temperatures of the first and second measurement points.
    Type: Application
    Filed: February 27, 2019
    Publication date: December 24, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Wataru SUGIMURA, Ryusuke YOKOYAMA, Toshiyuki FUJIWARA, Toshiaki ONO
  • Publication number: 20200399783
    Abstract: A convection pattern control method includes: heating a silicon melt in a quartz crucible using a heating portion; and applying a horizontal magnetic field to the silicon melt in the quartz crucible being rotated. In the heating of the silicon, the silicon melt is heated with the heating portion whose heating capacity differs on both sides across an imaginary line passing through a center axis of the quartz crucible and being in parallel to a central magnetic field line of the horizontal magnetic field when the quartz crucible is viewed from vertically above. In the applying of the horizontal magnetic field, the horizontal magnetic field of 0.2 tesla or more is applied to fix a direction of a convection flow in a single direction in a plane orthogonal to an application direction of the horizontal magnetic field in the silicon melt.
    Type: Application
    Filed: February 27, 2019
    Publication date: December 24, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Hideki SAKAMOTO, Wataru SUGIMURA, Ryusuke YOKOYAMA, Naoki MATSUSHIMA
  • Patent number: 10872768
    Abstract: Provided are an epitaxial silicon wafer which can reduce metal contamination by exerting higher gettering capability and a method of manufacturing the same. In a method of manufacturing an epitaxial silicon wafer which includes a silicon wafer, a first silicon epitaxial layer formed on the silicon wafer, a first modifying layer in which carbon is implanted in a surface layer portion of the first silicon epitaxial layer, and a second silicon epitaxial layer on the first modifying layer, the peak concentration of the oxygen concentration profile in the first modifying layer after formation of the second silicon epitaxial layer is set to 2×1017 atoms/cm3 or less and the oxygen concentration of the second silicon epitaxial layer is set to be equal to or less than the SIMS detection lower limit value.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: December 22, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Ayumi Masada
  • Patent number: 10871515
    Abstract: Provided is a method of measuring the Fe concentration in a p-type silicon wafer by the SPV method, by which the detection limit for the Fe concentration can be lowered, and the measurement can be performed in a short time. The measurement by the SPV method is performed in a measurement mode in which irradiation with a plurality of lights having mutually different wavelengths is performed during the same period under conditions where (i) Time Between Readings is 35 ms or more and 120 ms or less and Time Constant is 20 ms or more, or Time Between Readings is 10 ms or more and less than 35 ms and Time Constant is 100 ms or more, and (ii) Number of Readings is 12 times or less.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: December 22, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Shinya Fukushima, Masahiko Mizuta
  • Publication number: 20200392618
    Abstract: A method of controlling contamination of a vapor deposition apparatus includes: a wafer loading step of loading a wafer for contamination evaluation into a chamber of the vapor deposition apparatus; a heat treatment step of heat treating the wafer for contamination evaluation at a heat treatment temperature of 1190° C. or more at a hydrogen flow rate of 30 slm or less; a wafer unloading step of unloading the wafer for contamination evaluation from the inside of the chamber; and a wafer contamination evaluation step of evaluating a level of metal contamination of the wafer for contamination evaluation. In a method of producing an epitaxial wafer, epitaxial growth is performed using a vapor deposition apparatus whose contamination is controlled by the contamination controlling method.
    Type: Application
    Filed: December 4, 2018
    Publication date: December 17, 2020
    Applicant: SUMCO CORPORATION
    Inventor: Shota KINOSE
  • Patent number: 10867791
    Abstract: A manufacturing method of an epitaxial silicon wafer uses a silicon wafer containing phosphorus, having a resistivity of less than 1.0 m?·cm. The silicon wafer has a main surface to which a (100) plane is inclined and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°5? to 0°25? with respect to an axis orthogonal to the main surface. The manufacturing method includes: annealing the silicon wafer at a temperature from 1200 degrees C. to 1220 degrees C. for 30 minutes or more under argon gas atmosphere (argon-annealing step); etching a surface of the silicon wafer (prebaking step); and growing the epitaxial film at a growth temperature ranging from 1100 degrees C. to 1165 degrees C. on the surface of the silicon wafer (epitaxial film growth step).
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 15, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Naoya Nonaka, Tadashi Kawashima, Kenichi Mizogami
  • Patent number: 10861709
    Abstract: Provided is a method of evaluating the impurity gettering capability of an epitaxial silicon wafer, which allows for very precise evaluation of the impurity gettering behavior of a modified layer formed immediately under an epitaxial layer, the modified layer containing carbon in solid solution. In this method, a modified layer located immediately under an epitaxial layer, the modified layer containing carbon in solid solution, is analyzed by three-dimensional atom probe microscopy, and the impurity gettering capability of the modified layer is evaluated based on a three-dimensional map of carbon in the modified layer, obtained by the analysis.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 8, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Satoshi Shigematsu, Ryosuke Okuyama, Kazunari Kurita
  • Patent number: 10861990
    Abstract: A method of manufacturing an epitaxial silicon wafer that includes growing a silicon single crystal ingot doped with a boron concentration of 2.7×1017 atoms/cm3 or more and 1.3×1019 atoms/cm3 or less by the CZ method; producing a silicon substrate by processing the silicon single crystal ingot; and forming an epitaxial layer on a surface of the silicon substrate. During growing of the silicon single crystal ingot, the pull-up conditions of the silicon single crystal ingot are controlled so that the boron concentration Y (atoms/cm3) and an initial oxygen concentration X (×1017 atoms/cm3) satisfy the expression X??4.3×10?19Y+16.3.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 8, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Kazuhisa Torigoe, Toshiaki Ono
  • Patent number: 10858753
    Abstract: A silicon single crystal manufacturing method by a Czochralski method pulls up a silicon single crystal from a silicon melt in a quartz crucible while applying a magnetic field to the silicon melt. During a pull-up process of the silicon single crystal, the surface temperature of the silicon melt is continuously measured, and crystal growth conditions are changed based on a result of frequency analysis of the surface temperature.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: December 8, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Wataru Sugimura, Ryusuke Yokoyama, Mitsuaki Hayashi
  • Publication number: 20200381243
    Abstract: A manufacturing method of a wafer includes a first and a second resin-application grinding step, and a third surface-grinding step. The first step includes: a first formation step of forming a first coating layer; a first surface-grinding step of placing the wafer so that the first coating layer contacts a reference surface of a table and surface-grinding a first surface of the wafer; and a first removal step of removing the first coating layer. The second step includes: a second formation step of forming a second coating layer; a second surface-grinding step of placing the wafer so that the second coating layer contacts the reference surface and surface-grinding the second surface; and a second removal step of removing the second coating layer. In the third step, the wafer is placed so that the last surface-ground surface contacts the reference surface and a surface opposite the contacted surface is surface-ground.
    Type: Application
    Filed: February 21, 2018
    Publication date: December 3, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Toshiyuki TANAKA, Yasuyuki HASHIMOTO