Abstract: A handheld computing device is used to copy files from the screen of a fixed computer. The display of the handheld device is linked to that of the underlying computer and file and directory icons together with their underlying files are copied to the handheld device. Files from the handheld device can also be transferred to the fixed computer. When a user is running a program on the fixed computer, he may capture the state of that computer and transfer everything needed to permit execution of that program to continue uninterrupted on the handheld device. Thus files and executing programs may be lifted from the fixed computer and used on the handheld device.

Abstract: A method for postmortem object type identification. In one method embodiment, the present invention accesses a memory dump. Next, a portion of the memory dump is partitioned into a first group of known memory object types. Additionally, a portion of the memory dump is partitioned into a second group of unknown memory object types. A first pointer, pointing from one of the first group of known memory object types to one of the second group of unknown memory object types, is then utilized to automatically infer the memory object type of one of the second group of unknown memory object types. A second pointer, pointing from the inferred memory object type to one of the second group of unknown memory object types is utilized to automatically infer a memory object type of another one of the second group of unknown memory object types.

Abstract: A method and apparatus provides the capability for activating, i.e., annealing or ablating, LASER activated fuses from the back-side of an integrated circuit chip using multiple-photon absorption techniques that allow the absorbed LASER energy to be highly localized in three dimensions. According to the invention, the photons from the LASER have an energy less than the band gap energy of the substrate material, therefore absorption in areas of the substrate other than the focal point is avoided. According to the invention, objects such as LASER activated fuses that lie either within the integrated circuit substrate, or on the opposite surface, i.e., the active surface, of the integrated circuit substrate can be accessed and activated by the LASER energy. Consequently, using the method of the invention, LASER activated fuses can be activated after the integrated circuit chip has been mounted in a flip-chip configuration and/or as part of a Multiple-Chip-Module.

Abstract: A method for quantifying effects of resonance in an integrated circuit's power distribution network is provided. The power distribution network includes a first power supply line and a second power supply line to provide power to the integrated circuit. Test ranges are selected for two test parameters, reference voltage potential of a receiver and data transmission frequency of the integrated circuit. At each combination of the two test parameters, bit patterns are transmitted by the integrated circuit to the receiver. A comparison is made between the transmitted bits and the received bits to determine whether the transmitted bits were correctly received. The comparison may be used to determine and report a range of values for the reference voltage potential and data transmission frequency that allow the transmitted bits to be correctly received.

Abstract: A mechanism for reformatting a simple source code statement into a compound source code statement is provided. Tokens are identified in unformatted source code, which contains simple statements. A syntax tree is created from the identified tokens. The syntax tree is used to identify one or more simple statements. In processing a particular simple statement, potential statements are identified in the particular simple statement. A tree of blocks, which identifies block levels, is created from the potential statements. An intermediate textual representation is created where each of the potential statements is on a different line. Indentation levels, which correspond to the block levels in the tree of blocks, are associated with each of the potential statements. Formatted source code is created by inserting begin and end block indicators into the intermediate textual representation.

Abstract: A data transmission update technique for use in a low power mode and/or a low activity mode of a computer system or a portion thereof is provided. When in the low power mode and/or the low activity mode, the technique initiates a testing of data transmissions, the results of which are used to adjust the timing of data receipt such that accurate and timely date communications are facilitated.

Abstract: An electronic assembly includes a housing having a first portion and a remaining portion. The first portion includes a surface forming an outer wall of the housing. The electronic assembly also includes a component such as a CD ROM drive, for example, that may be mounted on the first portion of the housing. Further, at least one additional component, such as a motherboard, may be mounted on the remaining portion of the housing. The first portion of the housing is rotatably attached to the remaining portion of the housing. When the first portion of the housing is rotated into a closed position, the component and the additional component are positioned adjacent to each other. However, when the first portion of the housing is rotated into an open position, the component and the additional component are moved away from each other to allow access to the additional component.

Abstract: A graphics system invokes a dicing process if one or more edges of a triangle T have length greater than a maximum length (LMAX), invokes a central subdivision process if a coverage estimate for the triangle T is greater than a maximum coverage and all edges of triangle T have length less than or equal to LMAX, invokes rendering of a sequence of one or more single-layer triangles based on triangle T if the coverage estimate for triangle T is less than or equal to the maximum coverage and all edges have length less than or equal to LMAX. Said invocation of rendering of the sequence of single-layer triangles results in the application of a plurality of texture layers to samples corresponding to triangle T. The samples are stored in the TAB between the application of successive layers of said plurality of texture layers.

Abstract: In accordance with the principles of the present invention, management of a data replication system is provided by a three-tiered arrangement. The lowest, or agent, tier comprises Common Information Model (CIM) provider objects that reside in the hosts providing the data replication service and that can make method calls on the low-level kernel routines. The middle, or logic, tier is a set of federated Java beans that communicate with each other, with the management facades and with the upper tier of the system. The upper, or presentation, tier of the inventive system comprises web-based presentation programs that can be directly manipulated by management personnel to view and control the data replication system.

Abstract: A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master, generating a system clock signal, while the second clock board acts as a slave. The first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal. If the phase difference exceeds a limit, the first crystal clock signal may be inhibited, preventing the first clock board from generating the system clock signal. The second clock board may monitor the system clock board in reference to a feedback clock signal. If the second clock board detects a predetermined number of consecutive missing clock edges, it may enable a second crystal clock signal, which may be used to generate a system clock signal.

Abstract: A method and apparatus for performing fast clip-testing operations in a general purpose processor are provided. This is accomplished by executing a single instruction for comparing a first value x to a second value y and, as a result of the comparison, determining whether x is less than y and whether x is less than negative y. The values x and y are stored in respective source registers of the processor specified by the instruction. Finally, as a result of the determination, one or more binary values representing the results of the determination are inserted into a destination register of the processor also specified by the instruction. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute a clip-testing function with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function.

Abstract: A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Abstract: A garbage collector operates in multiple threads, and one thread can be parsing a region containing a free block while another thread is allocating space from that free block for an object being relocated to that region. The object being relocated may be an array object, for which the length determination is based on more than one word in the object; it may be based on a class-identifying word and a number-of-elements word. To prevent a parsing thread from parsing erroneously by reading both of those words between the relocating thread's writing one of them and writing the other, the relocating thread first writes into the classifying word a distinguished value from which a parsing thread can conclude that the values it reads in other fields of the block are not to be trusted.

Abstract: The present invention provides a method and apparatus for arbitrating master-slave transactions. The apparatus includes a slave device adapted to receive a first request from a first master device. The apparatus further includes a record of one or more previous requests from the first master device and at least one additional master device, wherein the slave device is adapted to grant the first request based upon the record.

Abstract: Methods and apparatus are disclosed for enabling nodes in a data network having interconnect links to continue to transmit data when a link fails. This is done in realtime, in a manner transparent to upper-level clients, and at a hardware level without software intervention. A method is described in which a data packet is received or stored in a transmitter buffer at an originating node having a failed link where the data packet is scheduled to use the failed link. The data packet is routed to a failover storage area. The failover storage area is a shared resource in the node and consists of two first-in, first-out stacks for processing and routing the failover data packets. If needed, an alternative link is selected for the data packet and the data packet is routed to a transmitter associated with the alternative link. An alternative link is selected using a primary and secondary routing table, also part of the shared resource of the node.

Abstract: An apparatus and method are disclosed that define a new, uniform I/O (input/output) interface architecture between the processor module and the motherboard of a computer system, and between the motherboard and expansion boards, via uniform connectors designed to work with the new architecture, such that many different pin-outs are available to the processor module, the interface being dynamically configurable by component control logic of the processor module. Positioning of supplemental connectors (e.g. for I/O or communications) on edges of the cards defines an unimpeded airflow path allowing for efficient cooling of the system.

Abstract: A data imaging system is managed by a three-tiered system. The lowest, or agent, tier comprises Common Information Model (CIM) provider objects that reside in the host providing the data imaging service and can make method calls on low-level kernel routines that implement the service. The middle, or logic, tier is a set of federated Java beans that communicate with each other, with the CIM providers and with the upper tier of the system and provide the business logic for the system. The upper, or presentation, tier of the inventive system comprises web-based presentation programs that can be directly manipulated by management personnel to view and control the system from virtually anywhere in the network.

Abstract: A method for protecting reliability of data associated with a data array is provided. The method initiates with defining state information associated with the data array. Then, crucial state information is identified from the state information. Next, a copy of the crucial state information is generated. Then, the state information and the copy of the crucial state information are protected. Next, a worst case state associated with non-crucial information is defined. In response to detecting an error associated with the non-crucial information, the method includes defaulting to the worst case state. A computer readable media and a shared memory multiprocessor chip are also provided.

Abstract: A system and method of resetting a jam latch circuit includes an activation device. The activation device having respective inputs coupled to each one of several data lines. A first reset device is also included and has a first control input coupled to an output of the activation device. The first reset device having a reset voltage source coupled to an input of the first reset device. A second reset device is also included and has a second control input coupled a control signal. The second reset device being coupled in series with the first reset device. A storage cell is coupled to an output of the second reset device.

Abstract: A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.