Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Abstract: Resource management for controlling allocation of a resource to competing computer processes is achieved through the use of a joining function. A resource manager is responsive to identification of a thread for a first process requesting allocation of the resource, when the resource is already allocated to a thread for a second process, to establish a joining function to the thread for the second process. The joining function is operable to notify the resource manager on termination of the thread for the second process. The resource manager can therefore be operable in response to termination of the thread for the second process to allocate the resource to the first process. The first and second processes can be call handling processes for telecommunications apparatus where the resource manager provides allocation of a telephony resource, such as a modem or network interface, to the competing call handling applications. A telephony interface and the applications can be implemented in the Java™ language.

Abstract: One embodiment of the present invention provides a system that facilitates implementing multi-mode specification-driven disassembler. During operation, the disassembler receives a machine-code version of a computer program. In order to disassemble a specific machine-code instruction from this machine-code version, the system compares the machine-code instruction against a set of instruction templates for assembly code instructions to identify a set of matching templates. Next, the system selects a matching template from the set of matching templates based on the state of a mode variable, which indicates a specificity mode for the disassembler. The system then disassembles the machine-code instruction using the operand fields defined by the matching template to produce a corresponding assembly code instruction.

Abstract: A circuit has been developed that reduces the effective strength of a keeper circuit during an interval in which at least one path of an evaluation circuit is sensitive to a keeper device. The keeper circuit includes a keeper gating device coupled to a keeper device that is responsive to a keeper control. The keeper device is sized to overcome leakage current in the evaluation circuit. In some configurations, the keeper circuit includes a weak keeper device that is minimally sized to overcome noise while the keeper device is effectively disabled. In some configurations, the reduction in effective strength of the keeper circuit occurs before arrival of the fastest signal coupled to a sensitive output path of the evaluation circuit and the effective strength is restored after arrival of the slowest signal coupled to the sensitive output path of the evaluation circuit.

Abstract: This functions maintains two trees: a fast access tree referring to memory blocks of a size most often requested, and a general access tree referring to memory blocks of a size less often requested. After satisfying a request for a memory block, the function adjusts the trees to ensure that the fast access tree refers to memory blocks of the size most often requested. By providing such functionality, the function improves its performance over time through self-adaptation.

Abstract: Described is a scheduling system that provides allocation of system resources of one or more processor sets among groups of processes. Each of the process groups is assigned a fixed number of shares, which is the number that is used to allocate system resources among processes of various process groups within a given processor set. The described fair share scheduler considers each processor set to be a separate virtual computer. Different process sets do not share processes, a particular process must execute on a single processor set. In another embodiment of the invention, each process group could be given a separate number of shares for each processor set. Percentage of the resources of the specific processor set allocated to processes of a process group is calculated as a ratio of the shares of the process group on the processor set to the total number of shares of active process groups operating in that set.

Abstract: Providing a contract between an application server and a resource adapter that allows the application server to manage the lifecycle of the resource adapter. When deploying a resource adapter (or during application server startup), an application server bootstraps a resource adapter instance in an appropriate address space. When a resource adapter is undeployed (or during application server shutdown), the application server notifies the resource adapter instance to stop functioning in order to allow safe unloading. The contract provides a mechanism for an application server to manage the lifecycle of a resource adapter instance, allowing an application server to bootstrap a resource adapter instance during resource adapter deployment or application server startup and to expose some of its useful facilities to the resource adapter instance. It also provides a mechanism to notify the resource adapter instance while it is undeployed or during an orderly shutdown of the application server.

Abstract: Improved techniques for representation of objects in a Java™ programming environment are disclosed. The techniques are highly suitable for representation of Java™ objects inside virtual machines, especially those that operate with limited resources (e.g., embedded systems). A cluster of Java™ object representations is disclosed. Each of the Java™ object representations provide a reference to a Java™ object and a reference to the class associated with the Java™ object. Accordingly, a two-tier representation is provided which allows efficient implementation of applications which need to access information regarding both Java™ objects and classes. As a result, quick access to information regarding Java™ objects can be achieved.

Abstract: The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool (120) to extract information associated with the inputs/outputs from a netlist. The information includes information associated with circuit devices directly connected to the inputs/outputs, particularly information related to device connectivity and the feature sizes of the device. Once the information is extracted, a capacitance determination element (130) aggregates the feature sizes of all the circuit devices connected to each respective input or output, to obtain aggregate feature sizes for each respective input/output. The aggregate feature size is used in determining the total capacitance of the input/output. The total capacitance thus determined can be provided to a timing analysis tool (140), which uses the total capacitance of each input or output to generate a timing model for the circuit.

Abstract: Error detection using data block mapping is provided. One method includes receiving a write request to write a user data block having a first block size, generating an error detection code for the user data block, appending the error detection code to the user data block to form an extended data block, and mapping the extended data block to a plurality of actual data blocks, each actual data block having a block size equal to the first block size.

Abstract: One embodiment of the present invention provides a system that facilitates identifying expansion cards installed in a computer system. The system operates by first examining a device tree for the computer system to identify nodes within the device tree that are associated with the computer expansion cards. Next, the system obtains a subset of parameters from the device tree that are associated with the computer expansion cards, and then performs a pattern match between the subset of parameters for each card and entries in an information file to identify each computer expansion card.

Abstract: A garbage collector collects a dynamically allocated heap by employing the train algorithm, in which “car” sections of a heap generation are organized in groups, or “trains.” When a car section comes up for collection, objects that it contains are evacuated if they are referred to by references located in cars not currently being collected. The cars to which they are evacuated belong to the trains that contain the references. The trains form a sequence in which their constituent cars are to be collected, and objects that are directly allocated in the generation are placed into trains that precede some existing train in the collection sequence.

Abstract: A distributed system provides for separate management of dynamic cluster membership and distributed data. Nodes of the distributed system may include a state manager and a topology manager. A state manager handles data access from the cluster. A topology manager handles changes to the dynamic cluster topology. The topology manager enables operation of the state manager by handling topology changes, such as new nodes to join the cluster and node members to exit the cluster. A topology manager may follow a static topology description when handling cluster topology changes. Data replication and recovery functions may be implemented, for example to provide high availability.

Abstract: A method for inserting a prefix, including traversing a trie node block structure to obtain a trie node block in which to insert the prefix, determining whether the trie node block is associated with a hash table, if the trie node block is not associated with a hash table: calculating a set of hash values for a trie node in the trie node block, and populating the hash table using the set of hash values calculated for the trie node, and inserting the prefix in an appropriate location in the hash table using at least one of the set of hash values associated with the trie node.

Abstract: A system and method for providing hot-swap status indication in a computer system having redundant power supplies. In one embodiment a system comprises an electrical subsystem that is powered by a first power supply and second power supply. The system further comprises a hot-swap indicator configured to provide a first user indication to indicate whether the first power supply is hot-swappable depending on whether the first power supply is operating at greater than a predetermined power capacity usage, such as fifty percent. The system may also include a second hot-swap indicator for the second power supply.

Abstract: The present invention provides a method and apparatus for error recovery in a system. The apparatus comprises a directory cache adapted to store at least one entry and a control unit. The control unit is adapted to determine if at least one uncorrectable error exists in the directory cache and to place the directory cache offline in response to determining that the error is uncorrectable. The method comprises detecting an error in data stored in a storage device in the system, and determining if the detected error is correctable. The method further comprises making at least a portion of the storage device unavailable to one or more resources in the system in response to determining that the error is uncorrectable.

Abstract: One embodiment of the present invention provides a system that operatively couples an integrated circuit with a microstrip transmission line through chip lamination. The system includes a first semiconductor die containing the integrated circuit, and a second semiconductor die containing the microstrip transmission line. Unlike metal lines in the integrated circuit, which have relatively small cross-sections, the microstrip transmission line has a cross-section that is large enough so that signal propagation is governed by inductance and capacitance (LC) instead of resistance and capacitance (RC). The first semiconductor die and the second semiconductor die are laminated together so that the integrated circuit on the first semiconductor die is operatively coupled with the microstrip transmission line in the second semiconductor die.

Abstract: Improved transposition of a matrix in a computer system may be accomplished while utilizing at most a single permutation vector. This greatly improves the speed and parallelability of the transpose operation. For a standard rectangular matrix having M rows and N columns and a size M×N, first n and q are determined, wherein N=n*q, and wherein M×q represents a block size and wherein N is evenly divisible by p. Then, the matrix is partitioned into n columns of size M×q. Then for each column n, elements are sequentially read within the column row-wise and sequentially written into a cache, then sequentially read from the cache and sequentially written row-wise back into the matrix in a memory in a column of size q×M. A permutation vector may then be applied to the matrix to arrive at the transpose. This method may be modified for special cases, such as square matrices, to further improve efficiency.

Abstract: A method for system management of configuration data used by server or groups of servers. In one embodiment, the present invention is comprised of providing information relative to components of the system being managed. A common language is utilized to express the information. An interface is provided to enable inputting of said information. The interface also enables management of the inputted information. In one embodiment, the information is validated during inputting. The validation of inputted information ensures that the information inputted is compliant with a schema of the information. In one embodiment, the information is comprised of defined tasks that are performed by the components of the system. The information is further comprised of specified configurations relative to the defined tasks. The information further comprises a declared schema for representing the information.

Abstract: A half-rail differential driver circuit comprises a differential line pair, a high line and a low line, that are charged to half a first supply voltage, typically VDD, by shorting the high output line to the low output line during the pre-charge phase. The half-rail data lines are then pulled up or down during the evaluation phase. Since, according to the present invention, the switching differentials are only half-rail, the coupling capacitance is reduced by half. In addition, since according to the invention, the half-rail differential driver circuit employs a differential line pair, the return path is confined within the differential line pair, virtually eliminating the loop area and therefore virtually eliminating inductive coupling.