Abstract: A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

Abstract: An optical transmitter for transmitting a first output data signal and a second output data signal, the optical transmitter comprising: a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive a first input data signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first input data signal and the second input data signal; a first electro-optical converter, the first electro-optical converter coupled to the latch, the first electro-optical converter operable to transmit the first output data signal; and a second electro-optical converter, the second electro-optical converter coupled to the latch, the second electro-optical converter operable to transmit the second output data signal.

Abstract: A virtual machine, such as a Java™ virtual machine, is configured to operate as a web server so that users, using a browser, can make general-purpose inquiries into the state of the virtual machine or, in some cases, mutate the state of the VM. A “browsable” VM contains a network traffic worker, such as an HTTP thread, a services library, and a VM operations thread, which is an existing component in most virtual machines. The network traffic worker and the VM operations thread communicate through a request data structure. The VM operations thread generates a reply to the request upon receiving a request data structure from the traffic worker. Such a reply can be in the form of an HTTP response containing HTML or XML pages. These pages are transmitted back to the browser/user by the network traffic worker.

Abstract: A garbage collector divides the garbage-collected heap into “cards.” It maintains a table containing a card-object table entry for each card. A card's entry contains information from which the collector can determine where any references in the card are located and thereby identify objects that may be reachable. Specifically, although each entry is smaller than a memory address, it has enough possible values to give the relative location of the object in which the associated card begins or to direct the collector to another entry for that information. But the entries are additionally grouped into sequences of contiguous entries that together are large enough to contain a complete address. When every card associated with a entry in a given (address-sized) entry sequence begins in the same object, that entry sequence is together given a value that the collector can recognize as indicating that object's absolute location.

Abstract: Apparatus forming a computer system or such-like is disclosed that includes a central processing unit (CPU) and a power supply unit. The CPU provides a digital voltage ID (VID) signal output indicative of the power supply voltage that it desires to receive. The power supply unit has a control input for receiving a digital VID signal from the CPU. The power output from the unit is then provided to the CPU at a voltage level in accordance with the received digital VID signal. A VID offset generator is interposed between the CPU and the power supply unit. This receives the digital VID signal from the CPU, and modifies it by applying a positive or negative offset. The modified digital VID signal is then passed to the power supply unit, which supplies a voltage to the CPU as per the modified VID signal, rather than the VID signal originally output by the CPU.

Abstract: A mechanism is disclosed for enabling efficient testing of a set of computer code. Untested code portions within a body of code are determined, and testing priorities are assigned to untested code portions according to how frequently the untested code portions are likely to be invoked during normal operation. More frequently invoked untested code portions are ranked higher than less frequently invoked untested code portions. The prioritized data may be used by a testing team to determine which additional tests should be created for effective and efficient testing of the body of code.

Abstract: A service processor is provided for a computer system that includes a host processor and the service processor. The service processor includes a management interface including a first port forming an external user interface and a second port forming an internal console interface. The service processor is operable to provide system management functions within the computer system. It is also operable to respond to external mode switching commands received via the user interface to operate one of two modes. The first mode is a management mode in which commands received via the user interface are processed by the service processor. The second mode is a console mode in which commands received via the user interface are passed by the service processor to the console interface for processing by the host processor. The service processor can be implemented by a dual-ported microcontroller.

Abstract: A system and method for testing an integrated circuit is provided. The illustrative embodiment provides a scan cell for use with automatic test pattern generation (ATPG). In the scan cell of the illustrative embodiment, a flip-flop is configured as a master storage element and a latch is configured as a slave storage element. During standard operating mode, the flip-flop and the latch operate as standard storage elements in the circuit. During a test mode, the flip-flop and the latch form a shift register for shifting test pattern data through the circuit to identify and detect any faults in the circuit design.

Abstract: A speech-translating remote control includes a microphone operable to receive speech command, thereby outputting a speech signal; an audio transmitter operably connected to the microphone to transmit an audio input signal to a host system based on the speech signal; a signal receiver to receive a command signal transmitted by the host transmitter; and a signal transmitter operably connected to the signal receiver to transmit a control signal to an appliance based on the command signal.

Abstract: The present invention is directed toward using patterns in APDU to perform identification data substitution. According to one or more embodiments of the present invention, a user inserts a smart card into a card reader connected to a client computing device. Then, the user enters a PIN. The PIN is embedded into an APDU which is sent to the card reader and is presented to the smart card. The APDU contains special patterns that specify to the card reader where and in what format the PIN should be embedded into a prototype APDU that is constructed in the card reader and presented to the card for verification.

Abstract: The present invention provides a system and method within a high availability network for monitoring and managing cluster membership. The cluster membership monitor provides the ability to maintain a list of current cluster members, monitor status of each peer node on the cluster, stay apprised of each nodes viability, elect a master node for the cluster when necessary, and coordinate reformation as members join and leave the cluster.

Abstract: A printed circuit board (PCB) having an integrated strain gage. In one embodiment, a PCB includes a component footprint suitable for mounting an electronic component. A strain gage is integrated into the PCB in a location under the component footprint. The strain gage includes at least one electrical conductor that is accessible for resistance measurements.

Abstract: By maintaining consistency of instruction or operation identification between code prepared for profiling and that prepared using profiling results, efficacy of profile-directed code optimizations can be improved. In particular, profile-directed optimizations based on stall statistics are facilitated in an environment in which correspondence maintained between (i) instructions or operations whose execution performance may be optimized (or which may provide an opportunity for optimization of other instructions or operations) and (ii) particular instructions or operations profiled.

Abstract: Embodiments of a system and method for providing class dependency graph-based class loading and reloading may be used to segregate namespaces in a graph-centric way, and may provide a set of normalized topologies that may be used to efficiently support hot-swapping of programmatic logic such as classes, applets, and beans, among other applications. Embodiments may provide a domain-independent, flexible and robust namespace segregation technique that is based on the dependency between the various classes and not on details like the roles the classes play. The problem of segregating namespaces is formulated as a graph theory problem, and a solution is sought through graph techniques. The graph may be normalized by identifying and grouping interdependent classes and non-interdependent classes in separate groups. A directed dependency relationship of the groups may be determined using the relationships between the member classes of the groups.

Abstract: Techniques are provided for controlling data access to maintain data integrity. A request is received to perform an action on a data element. The request is analyzed based on at least one data access rule associated with the data element. This analysis further utilizes a data structure model associated with the data element. The request is approved if the request satisfies the data access rule. The request is rejected if the request does not satisfy the data access rule.

Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Abstract: Disclosed are novel methods and apparatus for provision of efficient, effective, and/or flexible computer system layout and/or cooling configuration. In accordance with an embodiment of the present invention, a method of cooling a computer system is disclosed. The computer system may include a plurality of heat generating electrical components that require cooling. The method includes: providing at least two cooling fans arranged front to back of the computer system to create a push (inlet) and pull (outlet) airflow to cool the computer system and providing a plurality of temperature sensors located at various locations within the computer system to sense a local temperature.

Abstract: Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.

Abstract: A method for routing conductors in an integrated circuit design is disclosed, including the steps of determining the number of sensitive conductors requiring placement into quiet track locations, wherein a quiet track location is defined as any track location immediately adjacent to a stable conductor, determining the number of quiet track locations available in said integrated circuit design, and routing one or more sensitive conductors into one or more quiet track locations.