Abstract: A system and method for providing hot-swap status indication in a computer system having redundant power supplies. In one embodiment a system comprises an electrical subsystem that is powered by a first power supply and second power supply. The system further comprises a hot-swap indicator configured to provide a first user indication to indicate whether the first power supply is hot-swappable depending on whether the first power supply is operating at greater than a predetermined power capacity usage, such as fifty percent. The system may also include a second hot-swap indicator for the second power supply.

Abstract: A system and method for the static scheduling of test cases. A static scheduler is used to schedule the entire verification test of an integrated circuit in advance. The static scheduler is used in conjunction with a hardware description language (HDL) circuit design, a virtual test bench, and simulation software. The static scheduler is configured to assign test events to resources, or functional units, of the integrated circuit design. Events for a resource are assigned to available time slots, or cycles. During event scheduling, the static scheduler is configured to ensure that there are no resource conflicts for a given time slot. By scheduling all test events in advance, pitfalls associated with dynamic scheduling may be avoided, such as those associated with the use of semaphores. By avoiding the use of semaphores, complex test scenarios and boundary conditions may be more fully exercised, as resources will not be locked. This may allow a more thorough verification of an integrated circuit design.

Abstract: A multiprocessor computer system to selectively transmit address transactions using a broadcast mode or a point-to-point mode. Either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency. A node is formed by a group of clients which share a common address and data network. The address network determines whether a transaction is conveyed in broadcast mode or point-to-point mode. The address network includes a table with entries which indicate transmission modes corresponding to different regions of the address space within the node. Upon receiving a coherence request transaction, the address network may access the table to determine the transmission mode which corresponds to the received transaction. Network congestion may be monitored and transmission modes adjusted accordingly. When network utilization is high, the number of transactions which are broadcast may be reduced.

Abstract: A modular computer system may be provided. The modular computer system may comprise a carrier operable removably to receive a plurality of computer system modules therein. A plurality of information processing modules can be removably received in the carrier, each module may have a communications port operable to connect to a communications network internal to the carrier. The modular computer system may also comprise a switch operable to connect to the internal communications network to distribute information messages between the modules and to connect to an external communications network. An information distribution module may be provided removably received in the carrier operable connect to the internal communications network to receive an information message, to perform processing on the message to determine a destination, and to forward the message toward the determined destination via the internal communications network.

Abstract: A “lidless” integrated circuit package includes a support member that is arranged to support at least part of a load placed on the integrated circuit package. The support member has or is connected to a flexible support device that is in supportive contact with the load and that is designed to flex dependent on a position of the support member. The flexible support device substantially ensures that a plane of the surface of the flexible support device and a plane of a surface of a semiconductor die of the integrated circuit package are co-planar, thereby leading to a desirable load distribution within the integrated circuit package.

Abstract: Provided are a computer implemented method, system, and program for accessing information on a device. A first and second buffers are generated in a computer readable medium. The first buffer is indicated as a read buffer. Property values are returned from the buffer indicated as the read buffer in response to requests for property values for the device. The second buffer is indicated as a refresh buffer. Updates to the property values accessed from the device are written to the buffer indicated as the refresh buffer.

Abstract: A garbage collector collects at least a generation of a dynamically allocated heap in increments. In each increment, it identifies references located outside a collection set that refer to objects that belong to the collection set, and it evacuates the objects thus referred to before it reclaims the memory space that the collection set occupies. In some collection increments, references to collection-set objects are located both inside and outside the generation. The collector locates all such references, both those inside the generation and those outside it, before it evacuates any objects in response to any of them. By doing so, it is able to reduce the cost of locating references and evacuating objects.

Abstract: A system for providing service attribute information including a directory server containing a hierarchical data store associating users with service attributes through data inheritance, wherein the hierarchical data store includes an organization level and a role level, and attribute templates defined with respect to services and levels, an application for generating a query to the directory server for a service attribute of a particular user of the application, wherein the directory server, in response to the query, is for using inheritance rules from the hierarchical data store to determine and report a service attribute for the particular user of the application.

Abstract: Disclosed is a method for managing resource usage of a particular resource by a set of related code, such as code executed on behalf of a downloaded applet. A resource indicator is associated with the related code, and the resource indicator indicates an amount of resource usage of the particular resource by the related code. The resource indicator is updated when the related code increases or decreases its collective resource usage of the particular resource.

Abstract: According to the invention, a processing core that executes a compare instruction is disclosed. The processing core includes a register file, comparison logic, decode logic, and a store path. Included in the register file are a number of general-purpose registers. The general-purpose registers include a first input operand register, a second input operand register and an output operand register. Comparison logic is coupled to the register file. The comparison logic tests for at least two of the following relationships: less than, equal to, greater than and no valid relationship. The decode logic selects the output operand register from the plurality of general-purpose registers. The store path extends between the comparison logic and the selected output operand register.

Abstract: A method for marking a transaction, comprising defining an application as a plurality of states, wherein each of the plurality of states is associated with at least one transition, specifying a transaction set comprising at least one of the plurality of states, specifying a commit set comprising at least one of a plurality of states, and marking the transaction using a transaction marking procedure, wherein the transaction marking procedure marks the transaction based on the transaction set, the commit set, and at least one of the plurality of transitions.

Abstract: An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.

Abstract: A system that associates an identifier with an instance defined within an object-oriented programming system. The system generates an identifier for the instance and associates a new near object with the instance, wherein the new near object points to a class specifying behavior for the object. The system stores the identifier in the new near object, and sets a class pointer located within a header of the instance to point to the new near object. In this way, the class pointer indirectly points to the class for the object through the new near object. The system can lock the instance to facilitate exclusive access to the instance by copying a near object associated with the instance to a method activation on the execution stack, and setting the class pointer of the instance to point to the copy of the near object on the execution stack.

Abstract: A computer-implemented method and apparatus for indicating a failover data path in a graphical user interface environment is provided. The method includes graphically displaying at least one source device; graphically displaying at least one target device; graphically displaying a first data path between at least one source device and at least one target device; and in response to a failure in the first data path: graphically indicating the failure in the first data path; and graphically displaying a failover data path.

Abstract: A system and method for discovering nodes in an M×N torus interconnection fabric of nodes is provided. The method comprises probing an M×N torus interconnection fabric, wherein M and N are integer values and said interconnection fabric includes a first plurality of nodes forming an x-axis and a second plurality of nodes forming a y-axis; and identifying a location of a first node relative to the x and y axes. The computer system comprises an M×N array of nodes, wherein M and N are integer values; and a plurality of interconnects connecting the M×N array. A first plurality of nodes in the M×N array form an x-axis in the M×N array, a second plurality of nodes in the M×N array form a y-axis in the M×N array, and a first node in the M×N array is configured to probe the M×N array to identify a location of the first node relative to the x-axis and the y-axis.

Abstract: The invention relates to the processing of state information such as interrupt status in a hierarchical network of nodes having a tree configuration. There is a root node at the top of the hierarchy, one or more intermediate nodes, and a plurality of leaf nodes at the bottom of the hierarchy. Each leaf node is linked to the root node by zero, one or more intermediate nodes. Each leaf node maintains information about one or more interrupt states, and each intermediate node maintains information derived from the interrupt states of leaf nodes below it in the hierarchy. This interrupt information is then processed by navigating from the root node to a first leaf node having at least one set interrupt state which is then masked out. The status of any intermediate nodes between this first leaf node and the root node is then updated if appropriate to reflect the fact that the particular interrupt state at the first leaf node is now masked out.

Abstract: Apparatus is provided for reliably generating a random number sequence. The apparatus comprises a digital pseudo-random number sequence generator having a first output and an analog random number sequence generator having a second output. The pseudo-random number sequence on the first output and the random number sequence on the second output are combined using logic such as an exclusive-OR operation to generate an output number sequence.

Abstract: One embodiment of the present invention provides a system that solves an unconstrained interval global optimization problem specified by a function ƒ, wherein ƒ is a scalar function of a vector x=(x1, x2, x3, . . . xn). The system operates by receiving a representation of the function ƒ, and then performing an interval global optimization process to compute guaranteed bounds on a globally minimum value ƒ* of the function ƒ(x) and the location or locations x* of the global minimum. While performing the interval global optimization process, the system deletes all of part of a subbox X for which ƒ(x)>ƒ_bar, wherein ƒ_bar is the least upper bound on ƒ* that has been so far found. This is called the “ƒ_bar test”. The system applies term consistency to the ƒ_bar test over the subbox X to increase that portion of the subbox X that can be proved to violate the ƒ_bar test.

Abstract: One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.

Abstract: Various embodiments of systems and methods for performing write cache mirroring may involve accessing different mapped regions within a memory. The memory controller may automatically mirror write requests to another memory. Write requests targeting one mapped region may be verified such that local completion of the write indicates that the mirrored write has also completed. Write requests targeting another mapped region may be unverified. Unverified writes may be verified by performance of a verified write.