Abstract: One embodiment of the present invention provides a system that facilitates deploying components on a client. During operation, the system establishes a communication session through a network connection between the client and a server. Next, the system migrates components from the server to the client, wherein the components provide services and are able to use services provided by other components. Finally, the client installs the components on the client, thereby allowing the components to provide services on the client. Note that by supporting deployment of components on the client in this way, the system facilitates a unified component architecture across the client and the server.

Abstract: A garbage collector that operates in multiple threads divides a generation of a garbage-collected heap into heap sections, with which it associates respective remembered sets of locations where references to objects in those heap sections have been found. When such a heap section comes up for collection, each of a plurality of parallel garbage-collector threads that is processing its remembered set maintains a separate “popularity”—indicating count map, which includes an entry for each of a set of segments into which the collector has divided that heap section. The thread increments an entry in its count map each time it finds a reference to an object in the associated segment. If an object is located in a segment for which the associated count-map entry has exceeded a threshold, the thread evacuates the object in a manner different from that in which it evacuates objects not thus been found to be popular.

Abstract: A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition.

Abstract: A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may include one or more discrete surface mount components disposed on the substrate. The multi-lid semiconductor package may include a sealant between the one or more die lids and the one or more substrate lids and the substrate. The one or more die lids and the one or more substrate lids may differ in construction, design, placement, and/or thermal performance.

Abstract: A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled to the first semiconductor die is configured to couple power signals to the first semiconductor die. A flexibility compliance of at least one section of the cable is greater than a threshold value thereby allowing the module to be positioned in a mounting structure.

Abstract: An interconnect apparatus, for example a switch, supports PCI-Express. The apparatus has a first plurality of ports configurable as upstream ports, each connectable to a respective host, and at least one port configurable as a downstream port connectable to a device. The apparatus is operable to support sharing of the device resources between hosts.

Abstract: A system for providing a floating point remainder comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and the second floating point operand, respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the remainder of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: A method for dynamically changing a virtual network interface card (VNIC) binding. If the use of a hardware receive ring (HRR) is below the first threshold and the use of the software receive ring (SRR) is above the second threshold, then: binding the first VNIC to the SRR and the second VNIC to the HRR, removing the binding from the first VNIC to the HRR, removing the binding from the second VNIC to the SRR, and reprogramming a hardware classifier to send packets associated with the r VNIC to a second HRR and to send packets associated with the second VNIC to the HRR, reprogramming a software classifier to send packets associated with the first VNIC to the SRR, wherein the software classifier is associated with a soft ring (SR) and the SR is configured to obtain packets from the second HRR.

Abstract: A method of controlling bandwidth including receiving and classifying a packet, sending the packet to a hardware receive ring based on a classification of the packet, and sending, in accordance with an operating mode, the packet to a software receive ring, sending the packet from the software receive ring to a virtual network interface card, where the virtual network interface card is associated with a virtual machine, where the operating mode is adjusted to control the bandwidth consumed by the virtual machine.

Abstract: An abstraction layer is comprised in the operating system that represents the particulars of the PPMs. The abstractions in the abstraction layer are differentiated from one another by parameters representing the characteristics of the PPMs. The dispatcher uses the abstraction to balance processing loads when assigning execution threads to the PPMs. The assigning of the execution threads and the balancing of the processing loads is performed while taking account of the characteristics of the PPMs, such as shared resources and clock speed.

Abstract: A system that generates an electromagnetic interference (EMI) fingerprint for a computer system is presented. During operation, the system executes a load script on the computer system, wherein the load script includes a specified sequence of operations. Next, the system receives EMI signals generated by the computer system while executing the load script. The system then generates the EMI fingerprint from the received EMI signals.

Abstract: A method for approving a response or a decision of an observed node in a distributed system that includes generating at least one selected from the group consisting of the response and the decision by the observed node, forwarding the at least one selected from the group consisting of the response and the decision to at least one of the plurality of chaperones associated with the observed node based on a chaperone scheme, and approving the least one selected from the group consisting of the response and the decision by the plurality of chaperones using a chaperone voting policy and a chaperone approval policy to obtain at least one selected from the group consisting of a approved response and a approved decision, wherein the distributed system implements an overlay network for message delivery, and wherein the observed node and the plurality of chaperones communicate using the overlay network.

Abstract: A system that monitors electromagnetic interference (EMI) signals to facilitate proactive fault monitoring in a computer system is presented. During operation, the system receives EMI signals from one or more antennas located in close proximity to the computer system. The system then analyzes the received signals to proactively detect anomalies during operation of the computer system.

Abstract: An apparatus and a method are provided for generating a random number, wherein the randomness of the random number is derived from thermal noise present across a pair of resistors. Each of the pair of resistors is defined to receive a respective input voltage and add a respective noise component to the input voltage. The output from each resistor in the pair of resistors is amplified to generate a noisy analog voltage that includes a representation of the random noise components added by the pair of resistors. The randomly varying noisy analog voltage is used to control a voltage controlled oscillator (VCO). The VCO generates a random digital signal based on the randomly varying noisy analog voltage. The random digital signal generated by the VCO is used to set a number of bits for defining a random number.

Abstract: Improved performance of simulation analysis of a circuit with some non-linear elements and a relatively large network of linear elements may be achieved by systems and methods that partition the circuit so that simulation may be performed on a non-linear part of the circuit in pseudo-isolation of a linear part of the circuit. The non-linear part may include one or more transistors of the circuit and the linear part may comprise an RC network of the circuit. By separating the linear part from the simulation on the non-linear part, the size of a matrix for simulation on the non-linear part may be reduced. Also, a number of factorizations of a matrix for simulation on the linear part may be reduced. Thus, such systems and methods may be used, for example, to determine current in circuits including relatively large RC networks, which may otherwise be computationally prohibitive using standard simulation techniques.

Abstract: A video encoder/adapter comprises a virtual display module for partial rendering of a software application image. The virtual display module presents to the software application a virtual display device upon which the software application window is displayed. From the virtual display device, the user identifies one or more portions of the virtual software application window that are to be rendered on the actual display device.

Abstract: Some embodiments of the present invention provide a system that determines a center of rotation for a component in a computer system. During operation, the system measures a first acceleration of a first location on the component and a second acceleration of a second location on the component, wherein the first location and the second location are separated by a predetermined distance. Then, the system determines the center of rotation using the first acceleration, the second acceleration, and the predetermined distance.

Abstract: A computer system that schedules loads across a set of processor cores is described. During operation, the computer system receives thermal measurements from sensors associated with the set of processor cores, and removes noise from the thermal measurements. Then, the computer system analyzes thermal properties of the set of processor cores based on the thermal measurements. Next, the computer system receives a process to be executed, and schedules the process to be executed by at least one of the processor cores based on the analysis. This scheduling is performed in a manner that reduces spatial and temporal thermal variations in the integrated circuit.

Abstract: A method, computer program product, and system for providing launchable application source code are presented. A determination is made regarding which target platforms a launchable application executable will be run on. Once the platforms have been determined, a cross platform executable is generated using the launchable application source code. Platform specific executables are also generated for each selected platform. The cross platform executable is then combined with the platform specific executable for the platform to provide the platform independent launchable application. The platform specific executable is launched by an Operating System as part of a system service, such as a screensaver, and calls the cross platform executable which is executed on a virtual machine running on the platform.

Abstract: A system and a method for simultaneously managing a local transaction and a global transaction in an application server. In one embodiment, a system may manage a first transaction, from a first application component, as a local transaction and also manage a second transaction, from a second application component, as a global transaction. In one embodiment, the first transaction and the second transaction may be managed from the same instance of the application server.