Abstract: A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may include one or more discrete surface mount components disposed on the substrate. The multi-lid semiconductor package may include a sealant between the one or more die lids and the one or more substrate lids and the substrate. The one or more die lids and the one or more substrate lids may differ in construction, design, placement, and/or thermal performance.

Abstract: A method is provided for supporting device sharing between hosts via a bus fabric. A master host owns a device tree and provides IO services to at least one client host. The client host comprises generic device drivers and subscribes to IO services provided by the master host.

Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. However, certain features and capabilities that would be desirable for debugging programs executed using transactional memory are absent from conventional debuggers. Breakpointing is one example of a capability not well supported when conventional debugging technology is applied to transactional memory. We describe techniques by which a debugger may instrument code (or by which a TM library may provide functionality) to direct execution of an atomic block to a code path that facilitates breakpoint handling.

Abstract: A processor including general-purpose and cryptographic functionality, in which cryptographic operations are visible to user-specified software. According to one embodiment, a processor may include instruction execution logic configured to execute instructions specified by a user of the processor, where the instructions are compliant with a general-purpose instruction set architecture. The processor may further include a cryptographic functional unit configured to implement a plurality of cryptographic operations, and further configured to process the cryptographic operations independently of the instruction execution logic. A subset of the instructions may be executable to cause individual ones of the cryptographic operations to be processed by the cryptographic functional unit.

Abstract: A method for tracing an instrumented program involves triggering a probe in the instrumented program, obtaining an original instruction associated with the probe, storing the original instruction into a scratch space, storing a jump instruction for an architecture that supports pc-relative addressing into the scratch space, wherein the jump instruction includes a next program counter value, executing the original instruction in the scratch space using a thread, and executing the jump instruction in the scratch space using the thread.

Abstract: An electronic device includes a keypad portion having at least one multifunction key and a display area displaying screen views having one or more soft key labels corresponding to respective ones of the multifunction keys. A display enhancing assembly enhances display of the soft key labels and/or menus in a manner that actively induces and trains the user to properly operate the multifunction keys in association with corresponding soft key labels. The display enhancing assembly employs visual cues such as a videographic moving arrow, help text bubbles, a sliding in/out presentation of menus in a series of menus and automated relative enlarging of pertinent text and/or dimming of non-pertinent screen contents.

Abstract: One embodiment of the present invention provides a system that supports parallelized generic reduction operations in a parallel programming language, wherein a reduction operation is an associative operation that can be divided into a group of sub-operations that can execute in parallel. During operation, the system detects generic reduction operations in source code. In doing so, the system identifies a set of reduction variables upon which the generic reduction operation will operate, along with a set of initial values for the variables. The system additionally identifies a merge operation that merges partial results from the parallel generic reduction operations into a final result. The system then compiles the program's source code into a form which facilitates executing the generic reduction operations in parallel.

Abstract: A system and method for tracking responses to InfiniBand RDMA Reads. When an RDMA Read or Read request is issued by a transmit module, a receive module is informed of the packet sequence numbers (PSN) associated with the expected RDMA Read responses. The receive module maintains a linked list for each queue pair that issues RDMA Reads. Each entry in the linked list corresponds to one RDMA Read for the associated queue pair, and identifies the first and last PSN and includes a link to the next entry in the linked list. When the final RDMA Read response is received, the receive module notifies the transmit module, which can then retire the RDMA Read from its retry queue.

Abstract: A system that facilitates precise inter-chip alignment. The system includes a first integrated circuit chip, whose surface has etch pit wells. The system also includes a second integrated circuit chip, whose surface has corresponding etch pit wells that mate with the etch pit wells of the first integrated circuit chip. Spherical balls are placed in the etch pit wells of the first integrated circuit chip such that when the corresponding etch pit wells of the second integrated circuit chip are substantially aligned with the spherical balls, the spherical balls mate with the etch well pits of the second integrated circuit chip, thereby precisely aligning the first integrated circuit chip with the second integrated circuit chip.

Abstract: A secure data broker has been developed, which provides a restricted message based data exchange between a client application and a secured information resource by allowing registered or verified messages to be brokered across a security barrier. In some configurations, both requests and responses are validated and brokered across the security barrier. In other configuration, either requests or responses are validated. To support validation, messages are formatted in accordance with a predefined message specification for at least part of a transaction path between a client application and an information resource accessed by the client application.

Abstract: In general, in one aspect, the invention relates to a network interface card (NIC) aggregation framework, including a plurality of providers each configured to publish at least one port, a MAC client configured to send a packet to the at least one port, and a media access control (MAC) service module configured to map the at least one port to one of the plurality of providers, wherein the MAC service module comprises a client interface configured to interface with the MAC client and a provider interface configured to interface with each of the plurality of providers.

Abstract: A method of generating a correction signal for a voltage controlled oscillator (VCO) includes receiving a first signal in a correction current generator, changing a state of a first error signal substantially simultaneously with a first changing state of the first signal, receiving a second signal in the correction current generator, changing a state of a second error signal substantially simultaneously with a first changing state of the second signal, changing the state of the first error signal substantially simultaneously with a second changing state of the second signal, changing the state of the second error signal substantially simultaneously with a second changing state of the first signal, combining the first error signal and the second error signal to generate the correction signal substantially equal to a difference between the first error signal and the second error signal and applying the correction signal to a loop filter coupled to a correction signal input of the VCO.

Abstract: One embodiment of the present invention provides a system for reducing the latency in retrieving a web page. The system receives a request from a browser to retrieve a target web page, wherein the request is received at a proxy server, which can retrieve the target web page through a low-latency Internet connection. The system then forwards the request to a host server. After receiving components comprising the target web page, the system generates a substitute web page which includes a graphical image of the target web page, and transfers the substitute web page to the browser. If the browser has a high-latency Internet connection, delivering the substitute web page instead of the actual target web page can avoid the latency involved in transferring the components of the target web page individually through the high-latency Internet connection, each of which may involve a separate round-trip delay.

Abstract: An invention is disclosed for a computer protocol that facilitates provisioning services to client devices. The computer protocol includes discovery transactions that allow a client device to retrieve information regarding services available to the client device from a provisioning server. A service comprises a plurality of content files capable of being installed on the client device. The computer protocol also includes subscription transactions that allow the client device to manage content in service directories. A service directory comprises a plurality of services. Further included in the computer protocol are delivery transactions that allow the client device to downloading of data related to services.

Abstract: One embodiment of the present invention provides a system that reports reasons for failure during transactional execution. During operation, the system transactionally executes a block of instructions in a program. If the transactional execution of the block of instructions completes successfully, the system commits changes made during the transactional execution, and resumes normal non-transactional execution of the program past the block of instructions. Otherwise, if transactional execution of the block of instructions fails, the system discards changes made during the transactional execution, and records failure information indicating why the transactional execution failed.

Abstract: A system including a plurality of data units, wherein each of the plurality of data units is associated with a data thread, a plurality of storage engines configured to store the plurality of data units, and a data scheduler configured to schedule an action to perform on the plurality of data units using the data thread associated with each of the plurality of data units, wherein the data thread includes a data thread duration and a plurality of tuples, and wherein each of the plurality of tuples includes an attribute and an attribute duration.

Abstract: A cooling apparatus includes a heat pipe base covering a heat source; a heat sink with a plurality of heat sink fins; a plurality of heat pipes connecting the heat pipe base and the heat sink; and a magneto-hydrodynamic (MHD) pump assembly connected to the heat sink. In a method for cooling a heat source with heat pipes, magneto-hydrodynamic (MHD) fluid pipes, and a heat sink, the method includes transmitting heat from evaporating ends of the heat pipes connected to a heat source to condensing ends of the heat pipes connected to the heat sink; and circulating MHD fluid inside the MHD fluid pipes embedded in the heat sink to dissipate heat.

Abstract: A method for resetting a pin on an access card is disclosed. The method includes generating a server authentication (SA) public key and an SA private key and attempting a write of the SA public key to the access card over a non-secure channel. The method further includes determining if the access card currently contains an existing SA public key.

Abstract: A method for estimating a quality of code coverage of a test is described. The method includes training a neural network, using the neural network to generate a risk factor for each code element, and determining a coverage quality based on risk factors of executed code elements and risk factors of unexecuted code elements. The neural network is trained by inputting suggestive data as input and error severity data as output. Suggestive data may be data that correlates to a likelihood that a code element contains an error, and the error severity data is an evaluation of a severity of any error that was present in the code element. A coverage quality can be determined based on the risk factors of the code elements tested during the test and the risk factors of the code elements not tested during the test.

Abstract: An integrated circuit containing a communication channel is described. This communication channel includes: a transmit circuit configured to transmit signals; a link coupled to an output of the transmit circuit; a receive circuit coupled to the link; and a clamping circuit coupled to the link. Note that the transmit circuit is capacitively coupled to the receive circuit via the link. Furthermore, the clamping circuit is configured to compensate for leakage current on the link by maintaining a voltage on the link corresponding to a logical “1” or a logical “0.” This voltage is based on a history of the transmitted signals.