Abstract: The present invention defines a mechanism for automatic synchronization of scripting variables in an action tag extension facility. Attached to each action, there is a TagExtraInfo class that describes the action. The TagExtraInfo class knows the attributes of the class, including the names of the scripting variables introduced or modified by the action. At translation time, a tag handler accesses the information from the TagExtraInfo class for each tag in a page. At run time, a pageContext object is created containing a mapping of scripting variables to values. The values are visible to the scripting code, and the scripting code can modify the values. Also, the values are accessible by the action code. The action code can modify the values or create new values and assign the values to scripting variables so that the scripting code can modify them later. Thus, the present invention allows action tags to be created without explicit knowledge of the scripting language used to create a page.

Abstract: Techniques for assuring thread rendezvous for a plurality of threads executing in a computing system are disclosed. Techniques can be used to assure thread rendezvous for read-only code in a manner that is more efficient than polling techniques. A Light-weight, Yet Trappable On Demand (LYTOD) instruction can be generated for code that is executed by one or more threads. Typically, a LYTOD instruction is generated at critical points of the code in order to assure safe-point thread rendezvous. The LYTOD is a lightweight instruction that can change its behavior from a lightweight instruction to an instruction that causes a trap when executed. The LYTOD can, for example, be implemented as a read-from-memory instruction that operates to load a register with a content of a valid memory location.

Abstract: A system that includes an object store layer configured to store a plurality of objects, wherein each of the plurality of objects comprises a method, a communication layer configured to receive an event from a user and generate a task based on the event, and a simulation layer configured to retrieve one of the plurality of objects responsive to execution of the task and execute the method associated with the one of the plurality of objects.

Abstract: One embodiment of the present invention provides a system that achieves low gate leakage current in an integrated circuit during sleep mode. Upon entering sleep mode, the system reduces the power supply voltage applied to the integrated circuit to a low voltage level, wherein the low voltage level is low enough to provide a low gate leakage current, but is high enough to maintain state in the integrated circuit.

Abstract: A computer component cooling apparatus is described. The cooling apparatus may include a fan assembly. The fan assembly may be coupled to a computer chassis. A duct may be slidably coupled to the fan assembly. The duct may be positioned in at least two positions on the fan assembly without being uncoupled from the fan assembly. In a first position, the duct may direct a flow of air over one or more computer components. In a second position, the duct may allow access to the one or more of the computer components.

Abstract: Methods and apparatus for implementing a virtual machine that supports the execution of more than one application per virtual machine process are described. According to one aspect of the present invention, a computing system includes a processor, a memory, and a virtual machine that is in communication with the processor. The virtual machine is arranged to enable one or more jobs to run on the virtual machine, and is further arranged to create a heap in the memory for each job that runs on the virtual machine. In one embodiment, the virtual machine includes a jobs manager, a class manager, and a heap manager. In such an embodiment, the heap manager manages substantially all heaps in the memory that are created by the virtual machine.

Abstract: A process automation application, referred to as a commerce exchange server, for sending transaction messages between application programs uses a transaction definition data structure for specifying the component operations and processing logic that comprise the transaction. The data structure specifies one or more operations that constitute the transaction, instructions for producing the input data needed for each operation, and conditional logic for specifying constraints on the sequence of operation execution. The conditional logic may include one or more expressions, ranging from simple to complex, including variables, math operations and functions, that are evaluated using the inputs or outputs of one or more prior operations to determine execution order of subsequent operations. The transaction definition data structure may also provide for broadcast operations and for conditioning the success of their execution.

Abstract: A computing device including a method of adding to a directory information tree involving the steps of accessing a template name, reading a template according to the accessed template name, the template including structural information of the directory information tree, receiving a first set of attributes from an application program, the received first set of attributes not including a location within the directory information tree, constructing an entry including the received first set of attributes, and a destination location within the directory information, the destination location generated using the structural information, and adding the constructed entry to the directory information tree at the destination location.

Abstract: A computer system supports virtual memory and a paging mechanism. When a new process is created, this occupies one or more memory region. In one embodiment, at least a first memory region occupied by the process at a first virtual address has predefined, fixed, page characteristics (for example page size). It turns out that these are not optimum for the performance of the process. In order to address this, a routine in a shared library is invoked to copy the component from the first memory region into a second memory region. The second memory region either has different page characteristics from the first memory region (for example, a different page size), or is modifiable to have such different page characteristics. The second memory region is reallocated in virtual memory so that it replaces the first memory region at the first virtual address.

Abstract: A test mechanism for testing device driver hardening includes an intercept mechanism for intercepting device driver access calls from a device driver under test and an interface for configuring the intercept mechanism to inject faults according to a determined test pattern. This mechanism enables the arbitrary introduction of typical faults. These faults may be introduced totally asynchronously and so emulate real life. A test harness module can be linked in to a test build of the driver. The test harness can intercept all of the device access calls. It mimics the normal function of these calls accessing the offset address and propagating the appropriate data. A test application is able to interpret a test script and to compare device driver responses to injected faults.

Abstract: A computer system may include a directory, several active devices configured to access data, an address network configured to convey address packets point-to-point between the active devices and the directory, and a data network configured to convey data between the active devices and the directory. The address network may include a response virtual network configured to convey response packets and a multicast virtual network configured to convey invalidating packets. A first active device may be configured to transition an ownership responsibility for a coherency unit upon receipt of a response packet and to transition an access right to the coherency unit upon receipt of a corresponding data packet. The ownership responsibility for the coherency unit transitions at a different time than the access right to the coherency unit transitions.

Abstract: Various systems and methods for using a directory based coherency protocol in a system that employs a split ownership and access right cache coherence mechanism are disclosed. A computer system may include a directory, several active devices configured to access data stored, an address network configured to convey coherence requests point-to-point between the active devices and the directory, and a data network configured to convey data between the active devices. If at least one of a subset of the active devices has a shared access right to a requested coherency unit, the directory is configured to send an invalidating address packet to each of the active devices in the subset. The subset contains fewer than all of the active devices.

Abstract: A method of automatic configuration of field replaceable units in a system includes steps of accessing configuration management system (CMS) class information from a field replaceable unit (FRU) and using the accessed information for deriving an initial configuration for the FRU. The FRU can contain information defining one or more configuration management system classes for the FRU. One or more management classes may be identified for managing one or more resources for the FRU. The CMS class information is then be used to derive the initial configuration information for the FRU for managing the device(s) of that FRU. The CMS class information can be held in non-volatile memory in the FRU. This information can be read on inserting the FRU into the system and can be used to establish the initial configuration prior to full integration of the FRU into the system.

Abstract: A service discovery protocol may allow clients in a distributed computing environment to search for services. Service providers (or a listener agent) may respond to search requests by publishing or providing corresponding service advertisements or URIs to corresponding service advertisements. When a service provider responds to a discovery search request (either directly or through a listener agent), the provider may choose to publish a protected or an un-protected (complete) advertisement. A protected advertisement may include the set of information necessary to obtain a complete advertisement. Publishing a protected advertisement may force the client to obtain a valid credential from an authentication service before receiving the complete un-protected advertisement from the service provider. A complete un-protected advertisement is needed to create a message endpoint for accessing the service.

Abstract: A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined formats in which the plurality of operands are represented, and generates one or more control signals. The result assembler receives the control signals from the circuit, along with one or more inputs, and assembles a result.

Abstract: A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.

Abstract: Methods and systems in accordance with the present invention efficiently validate digital certificates by answering Online Certificate Status Protocol (“OCSP”) requests without Certificate Revocation Lists (“CRL”). During validation of digital certificates, these methods and systems speed transmission, reduce required bandwidth and reduce required data storage by eliminating the need for the transmission of lengthy CRLs from a Certificate Authority (“CA”) when verifying a digital certificate from a client. In one implementation, they send a Lightweight Directory Access Protocol (“LDAP”) database query to a CA directory server to determine and pinpoint the existence of a valid digital certificate and check its validity without receiving a long list of data, such as a CRL, from a CA.

Abstract: Methods and systems consistent with the present invention establish a virtual network on top of current IP network naming schemes. The virtual network uses a separate layer to create a modification to the IP packet format that is used to separate network behavior from addressing. As a result of the modification to the packet format, any type of delivery method may be assigned to any address or group of addresses. The virtual network also maintains secure communications between nodes, while providing the flexibility of assigning delivery methods independent of the delivery addresses.

Abstract: A processing unit is connectable to a communications network. The processing unit has a data carrier reader operable to read a network identity from a portable data carrier. The processing unit is operable on being powered up to check for the presence of a said data carrier, and when a data carrier is present to use the network identity from the data carrier for communicating via the network. The data carrier can be in the form of a card having readable storage, for example a portable storage device having a readable semiconductor memory of a type know, for example, as a smart card, or memory card. The processing unit may be arranged to use only the network address read from the data carrier, and, in the absence of such a data carrier to prevent access to the network. Access to the network can be achieved by aborting the power up of the processing unit. The processing unit may therefore access the network only when the network address is present in the carrier reader when the processing unit is powered up.

Abstract: A system and method for monitoring the performance of a computer system by dynamically interposing an instrumented trap table. A base address of a trap table, which may be contained in a trap base address register, may be changed to indicate an instrumented trap table. An instrumented trap table may gather a variety of statistics, including the type of trap and an entry timestamp. An instrumented trap table may then call a non-instrumented trap table to process the trap. A non-instrumented trap table may pass control back to the instrumented trap table to collect further statistics, for example an exit timestamp. An instrumented trap table may then return process flow to the calling routing. In this manner, useful performance statistics may be gathered while trap events are processed by regular, optimized software.