Abstract: A method and system is provided for customizing Java API implementations. A plurality of class files is obtained, wherein the class files are capable of being used together to provide a plurality of functional behaviors to an application. A feature marker is then associated with each of the class files based on a functionality provided by the class file. Each feature marker indicates a particular functionality provided by the plurality of class files. Particular class files are then selected from the plurality of class files based on the feature markers associated with the particular class files. The plurality of class files can comprise a first JAR file, and the selected class files can be used to generate a second JAR file. The second JAR file can also exclude class files that are not selected. Further, non-Java based native files, if any, utilized by the plurality of class files can also be customized to a subset of the original native files in a similar manner.

Abstract: A method and system for the smart prefetching of instructions is disclosed. The method includes computing an effective memory latency of a request for data and using the effective memory latency to compute an effective address from which to prefetch data.

Abstract: A method for merging a first object graph with a second object graph, including packaging the first object graph into an internal representation, wherein the internal representation includes an attribute value and an object identity for each of a plurality of objects in the first object graph, sending the internal representation to a receiver, traversing the internal representation by the receiver, updating an object instance in the second object graph with the attribute value from the internal representation, if the object identity corresponding to the object instance is found in an identity mapping table, creating and populating a new object instance with the attribute value from the internal representation, if the object identity corresponding to the new object instance is not found in the identity mapping table, and linking the new object instance to the second object graph.

Abstract: A method and apparatus for performing a built-in self-test (“BIST”) on an integrated circuit device are disclosed. A BIST controller comprises a logic built-in self-test (“LBIST”) engine capable of executing a LBIST and storing the results thereof and a multiple input signature register (“MISR”). The LBIST engine includes a LBIST state machine; and a pattern generator seeded with a first primitive polynomial. The MISR is capable of storing the results of an executed LBIST, the contents thereof being stored per a second primitive polynomial. A method for performing a LBIST comprises seeding a pattern generator in a LBIST engine with a first polynomial; executing a LBIST using the contents of the pattern generator; and storing the results of an executed LBIST in a MISR utilizing a second primitive polynomial.

Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.

Abstract: The present invention provides a method and apparatus for automatic accessibility assessment. One embodiment of the present invention automatically executes and tests the accessibility of a computer program. This embodiment analyzes the executing computer program to determine whether enough information is presented for assistive technologies to work properly with the computer program. Another embodiment manipulates the user interface by simulating interactions with assistive technologies. Thus, it is determined which portion of the computer program's functionality is reachable through interaction with the simulated assistive devices. One embodiment allows a user to select states for testing which are otherwise unreachable by the simulated assistive devices. The computer program's interactions with the simulated assistive devices are used to determine whether any accessibility failures exist in the computer program.

Abstract: A server blade may comprise a processor. The server blade may additionally comprise a removable media interface device. The server blade can be configured as a field replaceable unit.

Abstract: A data storage array employing block verification information to invoke initialization procedures. In one embodiment, a data storage subsystem includes a plurality of storage devices configured in an array and a storage controller coupled to the storage devices. The storage controller is configured to store data in the form of stripes where each stripe includes a plurality of data blocks stored across the plurality of storage devices. Each of the data blocks is associated with block verification information. Upon certain write operations, the storage controller is configured to initialize a given stripe in response to detecting a mismatch in the block verification information in at least one data block of the given stripe. In one particular implementation, the block verification contained in each of the data blocks includes a logical block address and/or a cyclic redundancy code.

Abstract: A dirty memory is operable to store dirty indicators, each dirty indicator being settable to a given value indicative that a page of memory associated therewith has been dirtied. The dirty indicators are stored in groups with each group having associated therewith a validity indicator computed from the dirty indicator values of the group. The control logic is operable on reading a group to compute a validity indicator value based on the dirty indicator values for the group to determine the integrity of the group. The integrity can be confirmed by comparing the computed validity indicator value to a validity indicator value read for the group. Where the value read and the value computed compare equal, it can be assumed that the dirty indicator values of the group are correct. Preferably the validity indicator is a parity indicator. Although parity does not provide for error correction, parity has the advantage that minimal overhead is needed for computation and storage.

Abstract: A hardware-based method for performing secure communications between an authorized computing platform (ACP) and a hardware component is provided. In this method, a secure communication path is established between the ACP and the hardware component. Thereafter, data transmitted over the secure communication path between the ACP and the hardware component is protected.

Abstract: A method for securing a computer boot is provided. In this method, integrity measurements of program code being loaded for execution are taken during the computer boot, and the integrity measurements are stored in a system board trusted platform module (SBTPM). Subsequently, the integrity measurements are transferred from the SBTPM to a trusted platform module peripheral (TPMP) when the TPMP is initialized and accessible. Systems for securing a computer boot are also described.

Abstract: Failed disk reconstruction time in a RAID storage system is decreased when dealing with non-catastrophic disk failures by using conventional parity reconstruction to reconstruct only that part of the disk that actually failed. The non-failed remainder of the failed disk is reconstructed by simply copying the good parts of the failed disk to the reconstructed copy. Since the good parts of the failed disk are simply copied, it is possible to reconstruct a failed disk even in the presence of disk failures in the secondary volumes. The copying and reconstruction starts at the stripe level, but may be carried out at the data block level if a reconstruction error occurs due to secondary media errors.

Abstract: A method for analyzing test coverage of a software application is provided. The method includes profiling an executable of the software application to generate application call trees. The method also includes profiling test cases used to test a production Java VM so as to generate test case call trees. Also included is comparing the application call trees with the test case call trees so as to identify gaps in the application call tree not covered by the test case call trees.

Abstract: Methods and apparatus for reducing the number of runtime checks performed during the execution of a virtual machine. According to one aspect of the present invention, a computer system includes a preloader, a compiler, and a virtual machine. The preloader is arranged to determine whether a bytecode makes an active reference to a class which requires an execution of a static initializer, and is also arranged to determine if the class has a superclass which requires the execution of the static initializer. The compiler is arranged to accept a source file generated by the preloader as input and to produce an object file, and the virtual machine is arranged to execute the object file.

Abstract: Methods and systems consistent with the present invention provide a Supernet, a private network constructed out of components from a public-network infrastructure. The Supernet provides flexible and dynamic mobility support. When a destination node moves to a new location, it automatically updates the sending nodes with its new IP address. The destination node can choose among a number of ways to update the sending nodes, providing flexibility not found in conventional networks. Thus, a node can change locations repeatedly and continue to communicate directly with other nodes without the use of a proxy or other middleman.

Abstract: Improved frameworks for loading and execution of portable, platform independent programming instructions within a virtual machine are disclosed. The improved frameworks provide a mechanism that will generally improve the runtime performance of virtual machines by eliminating the need to always traverse a constant pool at runtime to execute a Java instruction. In effect, the described system contemplates doing some extra work during the loading of a class into a virtual machine by obtaining the information from the constant pool during loading and representing that information in a form that can be used more efficiently at runtime. Accordingly, methods for creating data structures suitable for use by a virtual machine to execute load constant commands, as well as methods for execution of Java load constant instructions are disclosed.

Abstract: A method of rating a bug, including reporting the bug to a business entity by an interested party, entering information regarding the bug into a database, assigning a priority number for the bug, calculating a sigma number for the bug using the priority number, evaluating the bug to be fixed using the sigma number, and escalating the bug. A bug council rating apparatus, including a database to store the information entered using a graphical user interface, a priority number module configured to generate a priority number, and a sigma number module configured to generate a sigma number.

Abstract: A system and method for automatically creating information useable to access functionality of a backend computer system coupled to an application server. The method may operate to connect to the backend computer system and obtain information specifying functionality of the backend system. The information obtained may be analyzed programmatically, and new information may be programmatically created based on the analysis, wherein the programmatically created information is useable for accessing the functionality of the backend system. For example, where the functionality comprises a programmatically callable function, the information created may include information specifying the function name, names of input and output parameters, data types of the parameters, etc. The programmatically created information may be stored in a repository for use in accessing the functionality of the backend computer system from the application server.

Abstract: A sense amplifier pulse shaping circuit maintains a relationship between a sense amplifier enable signal and a sense amplifier equalization enable signal while disabling equalization prior to evaluation and disabling evaluation prior to equalization. In some embodiments of the present invention, a sense amplifier pulse shaper circuit generates a sense amplifier equalization control signal and a sense amplifier enable signal. The sense amplifier equalization control signal has a rising transition effectively earlier than the rising transition of the sense amplifier enable signal. The sense amplifier enable signal has a falling transition effectively earlier than the falling transition of the sense amplifier equalization control signal. The sense amplifier equalization signal is discharged into the sense amplifier enable signal.

Abstract: A video projector including a network adapter, a microprocessor physically and electrically coupled to the network adapter, a graphics adapter physically and electrically coupled to the microprocessor, a light valve physically and electrically coupled to the graphics adapter, and a light source physically coupled to the light valve. The video projector is operable to receive video data in digital form and the network adapter and the video projector is operable to transfer the video data to the microprocessor, the graphics adapter, and the light valve in digital form.