Abstract: One embodiment of the present invention provides a system that processes memory-access instructions in an object-addressed memory hierarchy. During operation, the system receives a load instruction to be executed, wherein the load instruction loads a data item from an object, and wherein the load instruction specifies an object identifier (OID) for the object and an offset for the data item within the object. Next, the system compares the OID and the offset for the data item against OIDs and offsets for outstanding store instructions in a store queue. If the offset for the data item does not match any of the offsets for the outstanding store instructions in the store queue, and hence no read-after-write (RAW) hazard exists, the system performs a cache access to retrieve the data item for the load instruction.

Abstract: In a generational, copying garbage collector, young generation collection may be made more efficient by dynamically measuring object survival rates as a function of “fine-grained” allocation age, and choosing, on the basis of these survival rates, part of the young generation that will be not be collected, but instead scanned for pointers to objects in the rest of the young generation. The rest of the young generation, including objects referenced by the pointers, is then collected.

Abstract: Provided is an apparatus and method for accelerating cryptographic hash computations. For example, in a cryptographic hash computation such as SHA-1, multiple execution units in a processor can process loosely coupled data. Specifically, after preprocessing a message with a particular bit length and parsing the padded message into multiple blocks, a first execution unit can begin processing the blocks for a message schedule computation. While the first block is processed, the first execution unit produces a partial result for the computation of the compression function in the second execution unit. By simultaneously processing the blocks on multiple execution units, the cryptographic hash computation performance can improve.

Abstract: A method and system for efficient implementation of a large store buffer within a processor includes a store buffer within a processor having a first component configured to hold a plurality of younger stores requested by the processor and a second component configured to hold a plurality of older stores. The first component is implemented as a small content addressable memory (CAM) and the second component includes a first-in-first-out (FIFO) buffer to hold the data and addresses of the plurality of older stores and an address disambiguator to hold the addresses of each of the plurality of older stores found in the FIFO buffer. The processor uses the small CAM to perform most of the store-to-load forwarding in a fast and efficient way thereby enhancing processor performance.

Abstract: A computer server system having a cooling mechanism, including a fan configured to cool the computer server system, wherein the computer server system includes a plurality of components, a first casing including the plurality of components and the fan, and a second casing including the fan, wherein the second casing includes a first bracket and a second bracket that latch together to enclose the fan, and wherein the second casing enclosing the fan is configured to provide complete isolation of the fan from the first casing.

Abstract: An air baffle with an integrated expansion card attachment is disposed in a computer for receiving an expansion card having a handle attached thereto. The air baffle includes a first wall including a first guide and a second guide projecting from a side surface of the first wall. The first guide a second guide form a transverse space therebetween. The air baffle includes a second wall parallel to the first wall disposed a distance from the first wall approximately equal to a width of the expansion card. The second wall includes a snap retainer having a projected portion thereof. The transverse space formed between the first and second guides of the first wall has a size approximately equal to a thickness of the expansion card such that a first end of the expansion card is firmly held by the first guide and the second guide when the expansion card is inserted into the transverse space.

Abstract: A method for provisioning a plurality of heterogeneous operating systems on a plurality of target hosts that includes for each of the plurality of target hosts, obtaining a type of operating system (OS) to be provisioned on the target host, populating an OS profile model based on the type of operating system obtained, activating a deployment service based on the type of operating system, and provisioning the target host using a deployment service and the OS profile model.

Abstract: A processing architecture supports executing instructions in parallel after identifying at least one level of dependency associated with a set of traces within a segment of code. Each trace represents a sequence of logical instructions within the segment of code that can be executed in a corresponding operand stack. Scheduling information is generated based on a dependency order identified among the set of traces. Thus, multiple traces may be scheduled for parallel execution unless a dependency order indicates that a second trace is dependent upon a first trace. In this instance, the first trace is executed prior to the second trace. Trace dependencies may be identified at run-time as well as prior to execution of traces in parallel. Results associated with execution of a trace are stored in a temporary buffer (instead of memory) until after it is known that a data dependency was not detected at run-time.

Abstract: One embodiment of the present invention provides a system that uses the Newton-Raphson technique to compute a square-root. During operation, the system receives a radicand b. Next, the system calculates the square root of b, ?{square root over (b)}, by first using the Newton-Raphson technique to find 1/?{square root over (b)}, and then multiplying 1/?{square root over (b)} by b to produce ?{square root over (b)}. While using the Newton-Raphson technique to find 1/?{square root over (b)}, the system first obtains an initial estimate x0 for 1/?{square root over (b)} and then iteratively solves the equation x i + 1 = x i ? ? ( 3 - bx i 2 2 ) .

Abstract: One embodiment of the present invention provides a system that uses the Newton-Raphson technique to perform a division operation. During operation, the system receives a numerator a and a denominator b. The system then divides a by b by first using the Newton-Raphson technique to calculate 1/b, and then multiplying 1/b by a to produce the result a/b. While using Newton-Raphson technique to find 1/b, the system first obtains an initial estimate x0 for 1/b and then iteratively solves the equation xi+1=xi(2?bxi). Each iteration involves: (1) using a multiplier circuit to multiply b by xi to compute bxi; (2) performing a bit-wise complement operation on bxi to compute 2?bxi, whereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation. (3) The system then uses the multiplier circuit to multiply xi by 2?bxi to compute xi(2?bxi).

Abstract: A method for creating a unified binary file that may be executed on a plurality of hardware platforms. The unified binary file includes hardware independent code and a plurality of hardware dependent binary files for a variety of hardware platforms. When the unified binary file is executed on a supported hardware platform, an appropriate hardware dependent file is identified and installed. A method for preparing a software package supported on a plurality of hardware platforms for distribution. A unified binary file is created for each corresponding file of the software package. Each unified binary file includes installation directory information and dependent file information.

Abstract: A support tray with fold-away handles is disclosed. When the support tray (which may be used to support a printed circuit board) is installed into a computer chassis, the handles are put into an upright position in which the handles extend above the support tray. In this position, the handles can be held by a user to easily lower the support tray into the chassis. When the support tray is not installed in a chassis (e.g. when the support tray is being shipped), the handles are put into a fold-away position in which the handles are situated underneath the support tray. This enables the support tray to maintain a low profile when the handles are not in use.

Abstract: A hardware finite state machine for facilitating the processing of an XML (Extensible Markup Language) document or other structured data stream. An accelerator is implemented in hardware to enable fast processing of a document (or a segment thereof). The accelerator includes a finite state machine that embodies a ternary CAM (Content-Addressable Memory) and associated RAM (Random Access Memory). Processing of the document is divided into multiple states, with each state transition defined by a markup delimiter that triggers the transition. The CAM is programmed with entries containing the processing states and, for each possible transition from that state, a pattern for matching delimiters that trigger the possible transitions. For a CAM entry matching the current processing state and a sequence of characters from the document, which may contain a delimiter, the associated RAM identifies the next state and any action to be taken (e.g., to shift the sequence of characters).

Abstract: In a computer system having a multithreaded application and a generational garbage collector that dynamically pre-tenures objects from a predetermined number of candidate allocation sites, allocated byte accounting is performed by each application thread using an array that contains a number of entries equal to the total number of candidate sites at any given time. Each array is indexed by a site number assigned to that site and contains a bytes allocated count for that site. At compilation time, object allocation code that is generated by the compiler is modified to update an array entry associated with a site number that is assigned when the site is selected as a candidate site. Since each array is local to the thread that contains it, each thread can write into its array without using atomic operations or locks.

Abstract: A computer server includes a printed circuit board and a fan. The printed circuit board includes electronic components and a handling device mounted thereon. The fan is arranged to blow air across the electronic components mounted on the printed circuit board. The handling device is disposed in a path of airflow of the fan. The handling device comprises an airflow opening.

Abstract: A method for private personal identification number (PIN) management includes receiving a first PIN, receiving a first key used to scramble a second PIN that has been validated, receiving a first scrambled PIN comprising the second PIN scrambled with the first key, scrambling the first PIN with the first key to create a second scrambled PIN and validating the first PIN based at least in part on whether the first scrambled PIN matches the second scrambled PIN.

Abstract: A method for limiting power consumption in a multiprocessor chip is provided. In this method, a read or write request is received by the memory controller, which controls a memory that is external to the multiprocessor chip. The memory controller includes a bank counter that keeps track of the number of read or write requests received by the memory controller. At every clock cycle, the bank counter value is compared with a threshold value to determine whether the counter value is equal to the threshold value. If the bank counter value is determined to be equal to the threshold value, then any subsequent incoming read or write requests are blocked. The bank counter value is incremented each time a read or write request is sent to the memory.

Abstract: One embodiment of the present invention provides a system that facilitates making the files permanently unreadable. During operation, the system encrypts a file with a key K at a file manager and then stores the encrypted file in non-volatile storage. Next, the system stores the key K in a key database located in volatile storage at the file manager. The system then encrypts the key database, and stores the encrypted key database in non-volatile storage. Additionally, a key that can be used to decrypt the encrypted key database is maintained by a key manager, and is not maintained in non-volatile form by the file manager. In this way, if the file manager crashes, losing the contents of its volatile storage, the file manager must interact with the key manager to decrypt the encrypted key database.

Abstract: A method for writing data to a storage pool includes receiving a write operation to write a logical block of data to the storage pool, determining a number (n?1) of physical blocks required to store the logical block of data, generating a parity block using the logical block of data, allocating n physical blocks in the storage pool, writing the parity block in the first of n allocated physical block, and writing the logical block of data across the remaining n?1 allocated physical blocks, where n is less than a number of disks in the storage pool, and where each of the n allocated physical blocks is located on a different disk in the storage pool.

Abstract: One embodiment of the present invention provides a system that determines the cause of a correctable memory error. First, the system detects a correctable error during an access to a memory location in a main memory by a first processor, wherein the correctable error is detected by error detection and correction circuitry. Next, the system reads tag bits for a cache line associated with the memory location, wherein the tag bits contain address information for the cache line, as well as state information indicating a coherency protocol state for the cache line. The system then tests the memory location by causing the first processor to perform read and write operations to the memory location to produce test results. Finally, the system uses the test results and the tag bits to determine the cause of the correctable error, if possible.