Abstract: A system and method are provided for dynamically determining the priority of requests for access to a resource taking into account changes in the access needs of a requesting agent over time. A requesting agent selects a priority level from a plurality of priority selections to include with a priority request to an arbiter. Work requests requiring the access to a resource may be stored in a work request queue. The priority level may be dynamic. The dynamic priority level enables the agent to sequentially increase or decrease the priority level of a priority request when threshold values representing the number of work requests in the work request queue are reached. The threshold values which cause the priority level to be increased may be higher than the threshold values which cause the priority level to be decreased to provide hysteresis. The dynamic priority level may, alternatively, enable the agent to start a timer for timing a pending priority request for a predetermined time period.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: A hardware verification method includes obtaining a set of packets to be driven by a device under test and obtaining a set of timing and relation criteria which determines a sequence in which the packets should be driven by the device under test. The method further includes starting multiple drive loops, each drive loop picking up a packet and forcing the device under test to drive the packet. The method further includes starting multiple expect loops, each expect loop determining when to expect a packet driven by the device under test and picking up the expected packet when it arrives. For each drive loop, the method confirms that the timing and relation criteria are satisfied prior to allowing the drive loop to force the device under test. For each expect loop, the method checks if the expected packet arrives within a specified time period and raises an error flag if the expected packet does not arrive within the specified time period.

Abstract: System and method for performing message logging for networked applications running on application servers. The application server may run a process referred to as a “logging service” that accepts requests from client processes to log messages regarding various types of runtime events or conditions. These client processes may include any of various types of processes, such as modules or components running on the application server. Any of various types of information may be recorded when a message is logged. For example, the information may include the date and time the message was created, the type of message, such as a warning message, an error message, etc., the message text to be recorded, the ID of a service or component requesting the message to be logged, or any of various other types of information. The logging service may also be operable to handle low-storage-space or out-of-storage space conditions.

Abstract: A method of joining a plurality of sheets by means of a blind rivet, comprises: (i) forming holes in the sheets and placing the sheets together so that the holes are in register and form a single hole therethrough; (ii) inserting a blind rivet into the hole formed in the sheets from a working side thereof, the blind rivet comprising a sleeve (1) positioned about a mandrel that has a head (4); and (iii) setting the rivet. The hole (24) is radially enlarged at the outwardly facing surface of at least the sheet on the blind side, and the sleeve of the rivet is deformed during setting to form a rivet joint in which no part of the rivet is proud of the outwardly facing surface (28) of the sheet at least on the blind side of the sheets. The method enables rivet joints to be formed in sheets, for example used in enclosures that house modules, where there is no space available for the set rivets to protrude.

Abstract: Methods of and apparatuses for performing electromigration risk analyses of power interconnect systems in integrated circuits employ a pseudo dynamic simulation model, whereby all transistor gates of a transistor network coupled to the power interconnect system are switched at the same time. To accomplish simultaneity in switching, a netlist characterizing the transistor network is altered in a manner that all gates are connected to a common input signal node. Time dependent currents drawn by transistors of the transistor network connected to the power interconnect system are determined. The time dependent currents and dimensional characteristics gleaned from the layout of the integrated circuit are used to calculate peak, average, or RMS current densities. The current densities are compared to electromigration rules to determine what areas of the power interconnect system may be in violation of the electromigration rules.

Abstract: A chassis for an electronic system. The chassis includes a recess therein for housing a plurality of cooling fans that are arranged in series and can be removed from the recess by sliding out of the recess in a direction across the direction of intended airflow. The assembly is arranged such that any of the fans can be removed and replaced without interrupting operation of the or any other fan. The recess and/or the fans have a seal to prevent or reduce bypass leakage of air around the fans.

Abstract: A circuit for controlling a bitline during a memory access operation is provided. The circuit includes a plurality of sub-arrays with each sub-array having a plurality of memory cells. Each of the memory cells is coupled to respective bitline columns. The circuit further includes a sensed output from one of the bitline columns, and a global bitline coupled to a same respective bitline column of each of the plurality of sub-arrays. Each global bitline includes a voltage swing limiter for limiting a voltage swing of the global bitline, and an n-type transistor. The n-type transistor has a gate, a first terminal, and a second terminal. The gate is coupled to the sensed output, the first terminal is coupled to the global bitline, and the second terminal is coupled to the voltage swing limiter.

Abstract: A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively.

Abstract: A label holder for labeling a rack-mounted computer system component is provided. The label holder includes an elongated body, a plurality of legs, and at least one retaining foot on at least one of the legs. Additionally, the holder may include one or more stiffening members and/or one or more shoulder ledges. The holder may be installed on a ventilation grating on a surface of the computer system component. The holder may be configured to allow air to flow between the holder and computer system component, so that cooling air is not prevented from flowing through the computer system component by the holder. At least one leg and/or the elongated body may be elastically deformable to allow at least one retaining foot to be engaged with an opening on the surface of the computer system component. Additionally, one or more of the retaining feet may have a beveled lower surface that may assist in installing the holder.

Abstract: A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.

Abstract: A system links architecture neutral code downloaded to a resource constrained computer. The code may be separated into one or more packages having one or more referenceable items. The system maps the one or more referenceable items into corresponding one or more tokens; orders the tokens to correspond to a run-time mode; downloads the packages to the resource constrained computer; and links the packages into an executable code using the ordered tokens.

Abstract: An invention is provided for abstracting physical devices in a system. The invention includes a physical device code segment capable of receiving device data from a physical device. In communication with the physical device code segment is a logical device code segment. The logical device code segment is capable of receiving the device data from the physical device code segment. An application code segment, which is capable of processing device data generated by the physical device, is in communication with the logical device code segment. In this manner, the application code segment can access the device data from the logical device code segment.

Abstract: Methods and apparatus for managing power of a computer system. Access to a device by a process that accesses the device but does not require user interaction to continue running is prevented during power management and when the device is powered off. Memory space is allocated in the computer system prior to the device being powered off. All access to the device is directed to the allocated memory space during the power management period.

Abstract: The illustrative embodiment of the present invention provides a method of inserting a software created virtual interface between the user of a host electronic device and a network storage medium. Data read and write requests are written to the virtual interface. The virtual interface is located on the host electronic device and allocates data to available storage mediums. Recovery and reconfiguration operations on the storage mediums holding stored data are hidden from the user by the virtual interface and may be performed contemporaneously with the user accessing the stored data.

Abstract: A computer system may include several client devices, a data network configured to transmit data packets between the client devices, a coherency mode storage unit configured to store an indication to control whether a given address packet is transmitted through the address network in a point-to-point mode or a broadcast mode, and an address network configured to transmit address packets between the client devices. The address network includes several address switches and implements a broadcast virtual network that transmits broadcast mode packets and a non-broadcast virtual network that transmits point-to-point mode packets. A first address switch is configured to select an address packet to output during each of several arbitration cycles and to prioritize selection of address packets in the broadcast virtual network over selection of address packets in the non-broadcast virtual network during a first portion of the arbitration cycles.

Abstract: A method and apparatus for providing error isolation in a multi-domain computer system. The system includes a plurality of system resources allocated to form at least a first and second domain. The system resources of the first domain perform a set of transactions independent from a set of transactions performed by the system resources of the second domain. The system further comprises at least one interface for coupling one system resource from the first domain and one system resource from the second domain. The at least one interface tracks the set of transactions performed by the one system resource of the first domain and the one system resource of the second domain independently from one another.

Abstract: One embodiment of the present invention provides a system that uses a shared library to facilitate sharing objects containing metadata. During operation, the system receives identifiers for a set of objects to be included in the shared library. Next, the system generates a shared library containing the set of objects. In doing so, the system configures a symbol table within the shared library to include an identifier for each object. The system then installs the shared library in a file system, and configures the file system so that the shared library file can be accessed through a set of symbolic names, wherein each object is associated with a different symbolic name. This allows each object in the shared library to be referenced through its own symbolic name. Note that the present invention uses the shared library mechanism in a manner which differs from its typical use (sharing compiled, executable code).

Abstract: A layout and a method for generating a mask for a capacitor are provided. The layout and the mask allow for the formation of the capacitor or an array of capacitors without phase conflict when using phase shift masks in an optical lithography fabrication process.

Abstract: In an object-oriented data processing system, methods and systems in accordance with the present invention provide a proxy class dynamically generated at runtime that implements a list of interfaces specified at runtime such that a method invocation through an interface on an instance of the class is encoded and dispatched uniformly to an object that performs the invocation of the requested method. The generation of the proxy class at runtime and the specification at runtime of the list of interfaces implemented by the proxy class allow the interfaces to be used to be chosen at runtime before generation of the proxy class. Since the proxy class does not need to be created before compile time, the interface list implemented by the proxy class does not need to be known at the time the source code is written.